401   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()  local
404   if (PredSU->NumSuccsLeft == 0) {  in ReleasePred()
406     dumpNode(*PredSU);  in ReleasePred()
411   --PredSU->NumSuccsLeft;  in ReleasePred()
416     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());  in ReleasePred()
421   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {  in ReleasePred()
422     PredSU->isAvailable = true;  in ReleasePred()
424     unsigned Height = PredSU->getHeight();  in ReleasePred()
428     if (isReady(PredSU)) {  in ReleasePred()
429       AvailableQueue->push(PredSU);  in ReleasePred()
433     else if (!PredSU->isPending) {  in ReleasePred()
434       PredSU->isPending = true;  in ReleasePred()
435       PendingQueue.push_back(PredSU);  in ReleasePred()
823   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()  local
824   if (PredSU->isAvailable) {  in CapturePred()
825     PredSU->isAvailable = false;  in CapturePred()
826     if (!PredSU->isPending)  in CapturePred()
827       AvailableQueue->remove(PredSU);  in CapturePred()
830   assert(PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&  in CapturePred()
832   ++PredSU->NumSuccsLeft;  in CapturePred()
1973       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()  local
1974       if (SUNumbers[PredSU->NodeNum] == 0) {  in CalcNodeSethiUllmanNumber()
1978           assert(It.SU != PredSU && "Trying to push an element twice?");  in CalcNodeSethiUllmanNumber()
1982         WorkList.push_back(PredSU);  in CalcNodeSethiUllmanNumber()
1996       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()  local
1997       unsigned PredSethiUllman = SUNumbers[PredSU->NodeNum];  in CalcNodeSethiUllmanNumber()
2100     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()  local
2103     if (PredSU->NumRegDefsLeft == 0) {  in HighRegPressure()
2106     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in HighRegPressure()
2149     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()  local
2152     if (PredSU->NumRegDefsLeft == 0) {  in RegPressureDiff()
2153       if (PredSU->getNode()->isMachineOpcode())  in RegPressureDiff()
2157     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in RegPressureDiff()
2192     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()  local
2195     if (PredSU->NumRegDefsLeft == 0) {  in scheduledNode()
2213     --PredSU->NumRegDefsLeft;  in scheduledNode()
2214     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;  in scheduledNode()
2215     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in scheduledNode()
2274     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()  local
2277     if (PredSU->NumSuccsLeft != PredSU->Succs.size())  in unscheduledNode()
2279     const SDNode *PN = PredSU->getNode();  in unscheduledNode()
2379     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()  local
2380     if (PredSU->getNode() &&  in hasOnlyLiveInOpers()
2381         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasOnlyLiveInOpers()
2383           cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveInOpers()
2450     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()  local
2451     if (PredSU->isVRegCycle) {  in resetVRegCycle()
2452       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&  in resetVRegCycle()
2998     SUnit *PredSU = nullptr;  in PrescheduleNodesWithMultipleUses()  local
3001         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
3004     assert(PredSU);  in PrescheduleNodesWithMultipleUses()
3008     if (PredSU->hasPhysRegDefs)  in PrescheduleNodesWithMultipleUses()
3011     if (PredSU->NumSuccs == 1)  in PrescheduleNodesWithMultipleUses()
3021     for (const SDep &PredSucc : PredSU->Succs) {  in PrescheduleNodesWithMultipleUses()
3041                << PredSU->NodeNum  in PrescheduleNodesWithMultipleUses()
3043     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {  in PrescheduleNodesWithMultipleUses()
3044       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
3048         Edge.setSUnit(PredSU);  in PrescheduleNodesWithMultipleUses()