Lines Matching refs:getOpcode
273 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
278 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
712 switch (StoreVal.getOpcode()) { in getStoreSource()
904 return Opcode == OpN->getOpcode(); in match()
928 if (auto RootMaskPos = ISD::getVPMaskIdx(Root->getOpcode())) in VPMatchContext()
932 ISD::getVPExplicitVectorLengthIdx(Root->getOpcode())) in VPMatchContext()
940 return OpVal->getOpcode() == Opc; in match()
942 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), in match()
948 unsigned VPOpcode = OpVal->getOpcode(); in match()
1097 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1105 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
1106 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
1113 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || in isSetCCEquivalent()
1170 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
1187 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
1196 (LD->getOperand(2).getOpcode() != ISD::TargetConstant || in canSplitIdx()
1214 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) in reassociationCanBreakAddressingModePattern()
1257 if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) in reassociationCanBreakAddressingModePattern()
1289 if (N0.getOpcode() != Opc) in reassociateOpsCommutative()
1306 if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() && in reassociateOpsCommutative()
1361 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC && in reassociateOpsCommutative()
1362 N01->getOpcode() == ISD::SETCC) { in reassociateOpsCommutative()
1405 if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc && in reassociateReduction()
1531 unsigned Opc = Op.getOpcode(); in PromoteOperand()
1598 unsigned Opc = Op.getOpcode(); in PromoteIntBinOp()
1666 unsigned Opc = Op.getOpcode(); in PromoteIntShiftOp()
1699 if (Op && Op.getOpcode() != ISD::DELETED_NODE) in PromoteIntShiftOp()
1715 unsigned Opc = Op.getOpcode(); in PromoteExtend()
1728 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); in PromoteExtend()
1746 unsigned Opc = Op.getOpcode(); in PromoteLoad()
1885 assert(N->getOpcode() != ISD::DELETED_NODE && in Run()
1886 RV.getOpcode() != ISD::DELETED_NODE && in Run()
1904 if (RV.getOpcode() != ISD::EntryToken) in Run()
1921 switch (N->getOpcode()) { in visit()
2092 assert(N->getOpcode() != ISD::DELETED_NODE && in combine()
2095 if (N->getOpcode() >= ISD::BUILTIN_OP_END || in combine()
2096 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { in combine()
2108 switch (N->getOpcode()) { in combine()
2137 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { in combine()
2144 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, in combine()
2190 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) in visitTokenFactor()
2219 switch (Op.getOpcode()) { in visitTokenFactor()
2305 switch (CurNode->getOpcode()) { in visitTokenFactor()
2390 if (N->getOpcode() == ISD::TRUNCATE) { in isTruncateOf()
2396 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
2449 if (N->getOpcode() == ISD::ADD) { in canFoldInAddressingMode()
2458 } else if (N->getOpcode() == ISD::SUB) { in canFoldInAddressingMode()
2489 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) in foldSelectWithIdentityConstant()
2497 unsigned Opcode = N->getOpcode(); in foldSelectWithIdentityConstant()
2522 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && in foldBinOpIntoSelect()
2526 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect()
2532 if (TLI.isCommutativeBinOp(BO->getOpcode())) in foldBinOpIntoSelect()
2542 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { in foldBinOpIntoSelect()
2558 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) in foldBinOpIntoSelect()
2625 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubBoolOfMaskedVal()
2631 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubBoolOfMaskedVal()
2635 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2639 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
2647 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2666 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && in foldAddSubOfSignBit()
2671 bool IsAdd = N->getOpcode() == ISD::ADD; in foldAddSubOfSignBit()
2675 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2753 if (N0.getOpcode() == ISD::SUB) { in visitADDLike()
2770 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
2834 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) in visitADDLike()
2838 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitADDLike()
2842 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) in visitADDLike()
2846 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) in visitADDLike()
2850 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2856 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2862 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2868 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && in visitADDLike()
2874 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && in visitADDLike()
2875 N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLike()
2877 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), in visitADDLike()
2881 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && in visitADDLike()
2895 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2916 if (N0.getOpcode() == ISD::ADD) { in visitADDLike()
2935 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLike()
2947 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitADDLike()
2983 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2990 if (N0.getOpcode() == ISD::ADD && in visitADD()
2991 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
2992 N1.getOpcode() == ISD::VSCALE) { in visitADD()
3000 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitADD()
3001 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
3009 if (N0.getOpcode() == ISD::ADD && in visitADD()
3010 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && in visitADD()
3011 N1.getOpcode() == ISD::STEP_VECTOR) { in visitADD()
3023 unsigned Opcode = N->getOpcode(); in visitADDSAT()
3070 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
3075 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { in getAsCarry()
3094 if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY && in getAsCarry()
3095 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) in getAsCarry()
3099 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) in getAsCarry()
3118 if (N1.getOpcode() == ISD::ZERO_EXTEND) in foldAddSubMasked1()
3121 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) in foldAddSubMasked1()
3126 if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE) in foldAddSubMasked1()
3147 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && in visitADDLikeCommutative()
3161 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && in visitADDLikeCommutative()
3171 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { in visitADDLikeCommutative()
3188 if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 && in visitADDLikeCommutative()
3199 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
3207 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADDLikeCommutative()
3217 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
3275 if (V.getOpcode() != ISD::XOR) in extractBooleanFlip()
3308 bool IsSigned = (ISD::SADDO == N->getOpcode()); in visitADDO()
3321 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitADDO()
3363 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
3393 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitADDE()
3477 if (Carry1.getOpcode() != ISD::UADDO) in combineUADDO_CARRYDiamond()
3486 if (Carry0.getOpcode() == ISD::UADDO_CARRY && in combineUADDO_CARRYDiamond()
3489 } else if (Carry0.getOpcode() == ISD::UADDO && in combineUADDO_CARRYDiamond()
3573 unsigned Opcode = Carry0.getOpcode(); in combineCarryDiamond()
3574 if (Opcode != Carry1.getOpcode()) in combineCarryDiamond()
3629 if (N->getOpcode() == ISD::AND) in combineCarryDiamond()
3651 if ((N0.getOpcode() == ISD::ADD || in visitUADDO_CARRYLike()
3652 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitUADDO_CARRYLike()
3745 if (N->getOpcode() != ISD::SUB || in foldSubToUSubSat()
3755 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in foldSubToUSubSat()
3764 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3774 if (Op1.getOpcode() == ISD::TRUNCATE && in foldSubToUSubSat()
3775 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
3779 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) in foldSubToUSubSat()
3782 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) in foldSubToUSubSat()
3808 if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) in visitSUB()
3849 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3852 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3873 if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && in visitSUB()
3881 if (N1S && N1S.getOpcode() == ISD::SUB && in visitSUB()
3892 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) in visitSUB()
3896 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) in visitSUB()
3900 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) in visitSUB()
3904 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) in visitSUB()
3908 if (N0.getOpcode() == ISD::ADD) { in visitSUB()
3915 if (N1.getOpcode() == ISD::ADD) { in visitSUB()
3922 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3929 if (N0.getOpcode() == ISD::SUB) { in visitSUB()
3936 if (N0.getOpcode() == ISD::ADD && in visitSUB()
3937 (N0.getOperand(1).getOpcode() == ISD::SUB || in visitSUB()
3938 N0.getOperand(1).getOpcode() == ISD::ADD) && in visitSUB()
3940 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), in visitSUB()
3944 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && in visitSUB()
3950 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
3956 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) in visitSUB()
3962 if (N1.getOpcode() == ISD::AND) { in visitSUB()
3976 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { in visitSUB()
3977 if (N1.getOperand(0).getOpcode() == ISD::SUB && in visitSUB()
3984 if (N1.getOperand(1).getOpcode() == ISD::SUB && in visitSUB()
4012 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && isOneOrOneSplat(N1)) { in visitSUB()
4029 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSUB()
4035 if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() && in visitSUB()
4042 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
4048 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSUB()
4057 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
4067 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { in visitSUB()
4088 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
4098 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
4104 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { in visitSUB()
4112 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4125 if (N1.getOpcode() == ISD::SHL) { in visitSUB()
4132 if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) && in visitSUB()
4162 if (N0.getOpcode() != Max || N1.getOpcode() != Min) in visitSUB()
4182 unsigned Opcode = N->getOpcode(); in visitSUBSAT()
4254 bool IsSigned = (ISD::SSUBO == N->getOpcode()); in visitSUBO()
4300 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) in visitSUBE()
4351 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); in visitMULFIX()
4502 if (N0.getOpcode() == ISD::SHL) { in visitMUL()
4514 if (N0.getOpcode() == ISD::SHL && in visitMUL()
4517 } else if (N1.getOpcode() == ISD::SHL && in visitMUL()
4530 if (N0.getOpcode() == ISD::ADD && in visitMUL()
4541 if (N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
4549 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitMUL()
4574 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
4626 unsigned Opcode = Node->getOpcode(); in useDivRem()
4660 if (User == Node || User->getOpcode() == ISD::DELETED_NODE || in useDivRem()
4666 unsigned UserOpc = User->getOpcode(); in useDivRem()
4696 unsigned Opc = N->getOpcode(); in simplifyDivRem()
4956 if (N1.getOpcode() == ISD::SHL) { in visitUDIVLike()
4994 unsigned Opcode = N->getOpcode(); in visitREM()
5039 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
5225 unsigned Opcode = N->getOpcode(); in visitAVG()
5269 unsigned Opcode = N->getOpcode(); in visitABD()
5342 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
5352 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
5459 bool IsSigned = (ISD::SMULO == N->getOpcode()); in visitMULO()
5482 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); in visitMULO()
5524 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) in isSaturatingMinMax()
5545 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { in isSaturatingMinMax()
5565 switch (N0.getOpcode()) { in isSaturatingMinMax()
5570 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5581 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
5626 if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) in PerformMinMaxFpToSatCombine()
5649 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || in PerformUMinFpToSatCombine()
5650 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) in PerformUMinFpToSatCombine()
5682 unsigned Opcode = N->getOpcode(); in visitIMINMAX()
5759 unsigned LogicOpcode = N->getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5760 unsigned HandOpcode = N0.getOpcode(); in hoistLogicOpWithSameOpcodeHands()
5762 assert(HandOpcode == N1.getOpcode() && "Bad input!"); in hoistLogicOpWithSameOpcodeHands()
6150 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && in foldAndOrOfSETCC()
6156 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || in foldAndOrOfSETCC()
6245 bool IsOr = (LogicOp->getOpcode() == ISD::OR); in foldAndOrOfSETCC()
6252 getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(), in foldAndOrOfSETCC()
6267 CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) && in foldAndOrOfSETCC()
6345 if (T.getOpcode() != ISD::AND) in combineSelectAsExtAnd()
6375 if (N1.getOpcode() == ISD::ADD) in visitANDLike()
6379 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
6551 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && in SearchForAndLoads()
6560 switch(Op.getOpcode()) { in SearchForAndLoads()
6584 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
6657 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6686 if (And.getOpcode() == ISD ::AND) in BackwardsPropagateMask()
6706 assert(N->getOpcode() == ISD::AND); in unfoldExtremeBitClearingToShifts()
6722 OuterShift = M->getOpcode(); in unfoldExtremeBitClearingToShifts()
6758 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); in combineShiftAnd1ToBitTest()
6762 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6779 if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6784 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6837 if (N0.getOpcode() == ISD::SRA) in foldAndToUsubsat()
6841 if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) in foldAndToUsubsat()
6844 if (N1.getOpcode() != ISD::SRA || !N0.hasOneUse() || !N1.hasOneUse() || in foldAndToUsubsat()
6868 unsigned LogicOpcode = N->getOpcode(); in foldLogicOfShifts()
6876 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6877 if (LogicOp.getOpcode() != LogicOpcode || in foldLogicOfShifts()
6889 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6893 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && in foldLogicOfShifts()
6916 unsigned LogicOpcode = N->getOpcode(); in foldLogicTreeOfShifts()
6919 if (LeftHand.getOpcode() != LogicOpcode || in foldLogicTreeOfShifts()
6920 RightHand.getOpcode() != LogicOpcode) in foldLogicTreeOfShifts()
7040 if (N0.getOpcode() == ISD::OR && in visitAND()
7044 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
7068 if (ISD::isExtOpcode(N0.getOpcode())) { in visitAND()
7069 unsigned ExtOpc = N0.getOpcode(); in visitAND()
7071 if (N0Op0.getOpcode() == ISD::AND && in visitAND()
7092 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
7094 N0.getOperand(0).getOpcode() == ISD::LOAD && in visitAND()
7096 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND()
7097 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? in visitAND()
7196 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
7197 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitAND()
7239 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) in visitAND()
7256 if (N0.getOpcode() == N1.getOpcode()) in visitAND()
7272 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { in visitAND()
7275 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
7278 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && in visitAND()
7314 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { in visitAND()
7333 if (LHS->getOpcode() != ISD::SIGN_EXTEND) in visitAND()
7379 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
7381 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7383 if (N0.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7396 if (N1.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7406 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7408 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
7422 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7433 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
7491 unsigned Opc = N.getOpcode(); in isBSwapHWordElement()
7496 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement()
7573 if (N.getOpcode() == ISD::OR) in isBSwapHWordPair()
7577 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
7595 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && in matchBSwapHWordOrAndAnd()
7599 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in matchBSwapHWordOrAndAnd()
7613 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
7666 } else if (N0.getOpcode() == ISD::OR) { in MatchBSwapHWord()
7713 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in visitORLike()
7739 if (N0.getOpcode() == ISD::AND && in visitORLike()
7740 N1.getOpcode() == ISD::AND && in visitORLike()
7758 if (V->getOpcode() == ISD::ZERO_EXTEND || V->getOpcode() == ISD::TRUNCATE) in visitORCommutative()
7764 if (N0Resized.getOpcode() == ISD::AND) { in visitORCommutative()
7791 if (N0.getOpcode() == ISD::XOR) { in visitORCommutative()
7801 if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { in visitORCommutative()
7813 if (V->getOpcode() == ISD::ZERO_EXTEND) in visitORCommutative()
7819 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
7825 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7969 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && in visitOR()
7985 if (N0.getOpcode() == N1.getOpcode()) in visitOR()
8017 if (Op.getOpcode() == ISD::AND && in stripConstantMask()
8029 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
8064 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
8078 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
8079 ExtractFrom.getOpcode() == ISD::ADD && in extractShiftForRotate()
8095 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; in extractShiftForRotate()
8096 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) in extractShiftForRotate()
8103 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
8104 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
8109 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || in extractShiftForRotate()
8232 if (Neg.getOpcode() != ISD::SUB) in matchRotateSub()
8267 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) in matchRotateSub()
8279 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { in matchRotateSub()
8352 if (Op.getOpcode() != BinOpc) in MatchFunnelPosNeg()
8379 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && in MatchFunnelPosNeg()
8418 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && in MatchRotate()
8464 if (LHSShift.getOpcode() == RHSShift.getOpcode()) in MatchRotate()
8468 if (RHSShift.getOpcode() == ISD::SHL) { in MatchRotate()
8475 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
8521 if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) in MatchRotate()
8590 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
8591 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
8592 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
8593 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && in MatchRotate()
8594 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || in MatchRotate()
8595 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
8596 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
8597 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { in MatchRotate()
8686 (Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector())) in calculateByteProvider()
8691 if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value()) in calculateByteProvider()
8701 switch (Op.getOpcode()) { in calculateByteProvider()
8747 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
8844 switch (Value.getOpcode()) { in stripTruncAndExt()
8937 if (Trunc.getOpcode() != ISD::TRUNCATE) in mergeTruncStores()
8943 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
9092 assert(N->getOpcode() == ISD::OR && in MatchLoadCombine()
9292 assert(N->getOpcode() == ISD::XOR); in unfoldMaskedMerge()
9304 if (And.getOpcode() != ISD::AND || !And.hasOneUse()) in unfoldMaskedMerge()
9307 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) in unfoldMaskedMerge()
9438 unsigned N0Opcode = N0.getOpcode(); in visitXOR()
9512 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && in visitXOR()
9519 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && in visitXOR()
9536 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { in visitXOR()
9575 if (N0Opcode == N1.getOpcode()) in visitXOR()
9610 unsigned LogicOpcode = LogicOp.getOpcode(); in combineShiftOfShiftedLogic()
9616 unsigned ShiftOpcode = Shift->getOpcode(); in combineShiftOfShiftedLogic()
9623 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) in combineShiftOfShiftedLogic()
9699 switch (LHS.getOpcode()) { in visitShiftByConstant()
9707 if (N->getOpcode() != ISD::SHL) in visitShiftByConstant()
9716 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || in visitShiftByConstant()
9717 BinOpLHSVal.getOpcode() == ISD::SRA || in visitShiftByConstant()
9718 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
9720 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
9721 BinOpLHSVal.getOpcode() == ISD::SELECT; in visitShiftByConstant()
9733 N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) { in visitShiftByConstant()
9734 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant()
9736 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
9743 assert(N->getOpcode() == ISD::TRUNCATE); in distributeTruncateThroughAnd()
9744 assert(N->getOperand(0).getOpcode() == ISD::AND); in distributeTruncateThroughAnd()
9794 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); in visitRotate()
9808 if (N1.getOpcode() == ISD::TRUNCATE && in visitRotate()
9809 N1.getOperand(0).getOpcode() == ISD::AND) { in visitRotate()
9811 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); in visitRotate()
9814 unsigned NextOp = N0.getOpcode(); in visitRotate()
9823 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()
9837 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), in visitRotate()
9868 if (N0.getOpcode() == ISD::AND) { in visitSHL()
9873 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
9892 if (N1.getOpcode() == ISD::TRUNCATE && in visitSHL()
9893 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSHL()
9899 if (N0.getOpcode() == ISD::SHL) { in visitSHL()
9929 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
9930 N0.getOpcode() == ISD::ANY_EXTEND || in visitSHL()
9931 N0.getOpcode() == ISD::SIGN_EXTEND) && in visitSHL()
9932 N0.getOperand(0).getOpcode() == ISD::SHL) { in visitSHL()
9963 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); in visitSHL()
9973 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
9974 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
9996 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
10022 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); in visitSHL()
10030 if (N0.getOpcode() == ISD::SRL && in visitSHL()
10058 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && in visitSHL()
10070 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && in visitSHL()
10079 if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint()) in visitSHL()
10081 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1, Flags); in visitSHL()
10088 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitSHL()
10089 N0.getOperand(0).getOpcode() == ISD::ADD && in visitSHL()
10095 if (SDValue ExtC = DAG.FoldConstantArithmetic(N0.getOpcode(), DL, VT, in visitSHL()
10099 SDValue ExtX = DAG.getNode(N0.getOpcode(), DL, VT, Add.getOperand(0)); in visitSHL()
10107 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { in visitSHL()
10123 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
10131 if (N0.getOpcode() == ISD::STEP_VECTOR && in visitSHL()
10149 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
10162 if (ShiftOperand.getOpcode() != ISD::MUL) in combineShiftToMULH()
10169 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH()
10170 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
10180 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { in combineShiftToMULH()
10211 if (LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
10255 bool IsSigned = N->getOpcode() == ISD::SRA; in combineShiftToMULH()
10262 unsigned Opcode = N->getOpcode(); in foldBitOrderCrossLogicOp()
10269 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) { in foldBitOrderCrossLogicOp()
10275 if (OldLHS.getOpcode() == Opcode && OldRHS.getOpcode() == Opcode) { in foldBitOrderCrossLogicOp()
10276 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), in foldBitOrderCrossLogicOp()
10280 if (OldLHS.getOpcode() == Opcode && OldLHS.hasOneUse()) { in foldBitOrderCrossLogicOp()
10282 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), in foldBitOrderCrossLogicOp()
10286 if (OldRHS.getOpcode() == Opcode && OldRHS.hasOneUse()) { in foldBitOrderCrossLogicOp()
10288 return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder, in foldBitOrderCrossLogicOp()
10326 if (N0.getOpcode() == ISD::SRA) { in visitSRA()
10344 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
10346 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
10362 if (N0.getOpcode() == ISD::SHL && N1C) { in visitSRA()
10402 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && in visitSRA()
10404 bool IsAdd = N0.getOpcode() == ISD::ADD; in visitSRA()
10406 if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && in visitSRA()
10443 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRA()
10444 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRA()
10453 if (N0.getOpcode() == ISD::TRUNCATE && in visitSRA()
10454 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
10455 N0.getOperand(0).getOpcode() == ISD::SRA) && in visitSRA()
10528 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
10553 if (N1C && N0.getOpcode() == ISD::TRUNCATE && in visitSRL()
10554 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
10593 if (N0.getOpcode() == ISD::SHL && in visitSRL()
10630 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitSRL()
10656 if (N0.getOpcode() == ISD::SRA) in visitSRL()
10662 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
10700 if (N1.getOpcode() == ISD::TRUNCATE && in visitSRL()
10701 N1.getOperand(0).getOpcode() == ISD::AND) { in visitSRL()
10747 if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) in visitSRL()
10750 if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND || in visitSRL()
10751 Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR) in visitSRL()
10768 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
10789 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, in visitFunnelShift()
10887 DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1})) in visitSHLSAT()
10894 if (N->getOpcode() == ISD::SSHLSAT && N1C && in visitSHLSAT()
10899 if (N->getOpcode() == ISD::USHLSAT && N1C && in visitSHLSAT()
10915 if (N->getOpcode() == ISD::TRUNCATE) in foldABSToABD()
10918 if (N->getOpcode() != ISD::ABS) in foldABSToABD()
10926 if (AbsOp1.getOpcode() != ISD::SUB) in foldABSToABD()
10932 unsigned Opc0 = Op0.getOpcode(); in foldABSToABD()
10936 if (Opc0 != Op1.getOpcode() || in foldABSToABD()
10988 if (N0.getOpcode() == ISD::ABS) in visitABS()
10999 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitABS()
11024 if (N0.getOpcode() == ISD::BSWAP) in visitBSWAP()
11031 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { in visitBSWAP()
11039 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { in visitBSWAP()
11061 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
11067 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
11087 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
11270 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
11302 if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) in shouldConvertSelectOfConstantsToMath()
11436 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
11474 if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) in foldVSelectToSignBitSplatMask()
11569 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { in visitSELECT()
11582 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { in visitSELECT()
11596 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { in visitSELECT()
11615 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { in visitSELECT()
11635 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
11655 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { in visitSELECT()
11712 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11713 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11714 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
11778 if (Index.getOpcode() != ISD::ADD) in refineUniformBase()
11802 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
11815 if (Index.getOpcode() == ISD::SIGN_EXTEND && in refineIndexType()
11911 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
11945 if (N->getOpcode() != ISD::DELETED_NODE) in visitMSTORE()
11955 if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && in visitMSTORE()
12175 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
12183 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) in visitVSELECT()
12186 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) in visitVSELECT()
12231 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && in visitVSELECT()
12253 if (N1.getOpcode() == ISD::SUB && N2.getOpcode() == ISD::SUB && in visitVSELECT()
12293 if (Other && Other.getOpcode() == ISD::ADD) { in visitVSELECT()
12310 if (OpRHS.getOpcode() == CondRHS.getOpcode() && in visitVSELECT()
12311 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12312 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
12344 if (Other && Other.getOpcode() == ISD::TRUNCATE && in visitVSELECT()
12345 Other.getOperand(0).getOpcode() == ISD::SUB && in visitVSELECT()
12349 if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) in visitVSELECT()
12364 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) in visitVSELECT()
12367 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12368 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12369 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12370 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12379 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && in visitVSELECT()
12392 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && in visitVSELECT()
12421 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12422 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12474 if (SCC.getOpcode() == ISD::SETCC) { in visitSELECT_CC()
12496 N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; in visitSETCC()
12507 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { in visitSETCC()
12534 return A.getOpcode() == ISD::AND && in visitSETCC()
12535 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) && in visitSETCC()
12539 return (B.getOpcode() == ISD::ROTL || B.getOpcode() == ISD::ROTR) && in visitSETCC()
12582 unsigned ShiftOpc = ShiftOrRotate.getOpcode(); in visitSETCC()
12678 unsigned Opcode = N->getOpcode(); in tryToFoldExtendSelectLoad()
12687 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
12708 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && in tryToFoldExtendSelectLoad()
12725 unsigned Opcode = N->getOpcode(); in tryToFoldExtendOfConstant()
12742 if (N0->getOpcode() == ISD::SELECT) { in tryToFoldExtendOfConstant()
12820 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
12843 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
12852 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
12892 assert((N->getOpcode() == ISD::SIGN_EXTEND || in CombineExtLoad()
12893 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
12913 if (N0->getOpcode() != ISD::LOAD) in CombineExtLoad()
12925 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) in CombineExtLoad()
12929 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
12980 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); in CombineExtLoad()
12988 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
12996 if (!ISD::isBitwiseLogicOp(N0.getOpcode()) || in CombineZExtLogicopShiftLoad()
12997 N0.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
12998 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
13003 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
13004 N1.getOperand(1).getOpcode() != ISD::Constant || in CombineZExtLogicopShiftLoad()
13005 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) in CombineZExtLogicopShiftLoad()
13020 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) in CombineZExtLogicopShiftLoad()
13037 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, in CombineZExtLogicopShiftLoad()
13042 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, in CombineZExtLogicopShiftLoad()
13066 unsigned CastOpcode = Cast->getOpcode(); in matchVSelectOpSizesWithSetCC()
13080 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
13081 VSel.getOperand(0).getOpcode() != ISD::SETCC) in matchVSelectOpSizesWithSetCC()
13212 assert((N->getOpcode() == ISD::SIGN_EXTEND || in foldExtendedSignBitTest()
13213 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
13216 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || in foldExtendedSignBitTest()
13239 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
13248 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
13322 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) in foldSextSetcc()
13389 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitSIGN_EXTEND()
13394 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND()
13395 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitSIGN_EXTEND()
13400 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSIGN_EXTEND()
13403 if ((N00.getOpcode() == ISD::TRUNCATE || TLI.isTruncateFree(N00, ExtVT)) && in visitSIGN_EXTEND()
13410 if (N0.getOpcode() == ISD::TRUNCATE) { in visitSIGN_EXTEND()
13483 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && in visitSIGN_EXTEND()
13485 N0.getOperand(1).getOpcode() == ISD::Constant && in visitSIGN_EXTEND()
13486 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitSIGN_EXTEND()
13500 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND()
13544 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in visitSIGN_EXTEND()
13546 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
13553 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && in visitSIGN_EXTEND()
13555 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
13594 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
13595 Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); in widenCtPop()
13598 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) in widenCtPop()
13616 assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend."); in widenAbs()
13623 if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse()) in widenAbs()
13658 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
13663 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitZERO_EXTEND()
13664 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) in visitZERO_EXTEND()
13690 if (N0.getOpcode() == ISD::TRUNCATE) { in visitZERO_EXTEND()
13734 if (N0.getOpcode() == ISD::AND && in visitZERO_EXTEND()
13735 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitZERO_EXTEND()
13736 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
13766 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && !TLI.isZExtFree(N0, VT) && in visitZERO_EXTEND()
13768 N0.getOperand(1).getOpcode() == ISD::Constant && in visitZERO_EXTEND()
13769 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { in visitZERO_EXTEND()
13777 if (N0.getOpcode() == ISD::AND) { in visitZERO_EXTEND()
13794 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
13831 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
13877 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
13882 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { in visitZERO_EXTEND()
13883 if (N0.getOpcode() == ISD::SHL) { in visitZERO_EXTEND()
13897 return DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND()
13932 if (N0.getOpcode() == ISD::ANY_EXTEND || in visitANY_EXTEND()
13933 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
13934 N0.getOpcode() == ISD::SIGN_EXTEND) in visitANY_EXTEND()
13935 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
13940 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitANY_EXTEND()
13941 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG || in visitANY_EXTEND()
13942 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in visitANY_EXTEND()
13943 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitANY_EXTEND()
13947 if (N0.getOpcode() == ISD::TRUNCATE) { in visitANY_EXTEND()
13960 if (N0.getOpcode() == ISD::TRUNCATE) in visitANY_EXTEND()
13965 if (N0.getOpcode() == ISD::AND && in visitANY_EXTEND()
13966 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && in visitANY_EXTEND()
13967 N0.getOperand(1).getOpcode() == ISD::Constant && in visitANY_EXTEND()
14017 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && in visitANY_EXTEND()
14033 if (N0.getOpcode() == ISD::SETCC) { in visitANY_EXTEND()
14087 unsigned Opcode = N->getOpcode(); in visitAssertExt()
14093 if (N0.getOpcode() == Opcode && in visitAssertExt()
14097 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
14098 N0.getOperand(0).getOpcode() == Opcode) { in visitAssertExt()
14117 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && in visitAssertExt()
14118 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
14148 switch (N0.getOpcode()) { in visitAssertAlign()
14163 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); in visitAssertAlign()
14176 unsigned Opc = N->getOpcode(); in reduceLoadWidth()
14254 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
14302 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
14324 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in reduceLoadWidth()
14432 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
14441 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { in visitSIGN_EXTEND_INREG()
14453 if (ISD::isExtVecInRegOpcode(N0.getOpcode())) { in visitSIGN_EXTEND_INREG()
14458 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in visitSIGN_EXTEND_INREG()
14470 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
14494 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
14579 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { in visitSIGN_EXTEND_INREG()
14589 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && in visitSIGN_EXTEND_INREG()
14590 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { in visitSIGN_EXTEND_INREG()
14612 unsigned InregOpcode = N->getOpcode(); in foldExtendVectorInregToExtendOfSubvector()
14626 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) in foldExtendVectorInregToExtendOfSubvector()
14648 return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG in visitEXTEND_VECTOR_INREG()
14677 if (N0.getOpcode() == ISD::TRUNCATE) in visitTRUNCATE()
14685 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
14686 N0.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
14687 N0.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
14690 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); in visitTRUNCATE()
14701 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitTRUNCATE()
14713 if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) in visitTRUNCATE()
14726 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
14752 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { in visitTRUNCATE()
14764 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && in visitTRUNCATE()
14790 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && in visitTRUNCATE()
14806 if (N0.getOpcode() == ISD::SPLAT_VECTOR && in visitTRUNCATE()
14820 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitTRUNCATE()
14821 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
14847 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
14867 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
14912 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { in visitTRUNCATE()
14934 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
14936 if (N00.getOpcode() == ISD::SIGN_EXTEND || in visitTRUNCATE()
14937 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
14938 N00.getOpcode() == ISD::ANY_EXTEND) { in visitTRUNCATE()
14953 switch (N0.getOpcode()) { in visitTRUNCATE()
14966 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { in visitTRUNCATE()
14970 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); in visitTRUNCATE()
14981 if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) || in visitTRUNCATE()
14982 TLI.isOperationLegal(N0.getOpcode(), VT)) && in visitTRUNCATE()
14988 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); in visitTRUNCATE()
14996 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitTRUNCATE()
14999 hasOperation(N0.getOpcode(), VT)) { in visitTRUNCATE()
15011 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
15019 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
15072 switch (N0.getOpcode()) { in foldBitcastedFPLogic()
15096 if (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).getValueType() == VT) in foldBitcastedFPLogic()
15113 if (N0.getOpcode() == ISD::OR) in foldBitcastedFPLogic()
15138 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && in visitBITCAST()
15160 if (N0.getOpcode() == ISD::BITCAST) in visitBITCAST()
15165 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() && in visitBITCAST()
15168 return (V.getOpcode() == ISD::BITCAST && in visitBITCAST()
15174 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, in visitBITCAST()
15219 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
15220 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
15232 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
15236 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15251 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
15254 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
15270 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitBITCAST()
15334 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
15343 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && in visitBITCAST()
15351 if (Op.getOpcode() == ISD::BITCAST && in visitBITCAST()
15406 bool AllowMultipleMaybePoisonOperands = N0.getOpcode() == ISD::BUILD_VECTOR || in visitFREEZE()
15407 N0.getOpcode() == ISD::BUILD_PAIR || in visitFREEZE()
15408 N0.getOpcode() == ISD::CONCAT_VECTORS; in visitFREEZE()
15430 if (MaybePoisonOperand.getOpcode() == ISD::UNDEF) in visitFREEZE()
15436 if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE && in visitFREEZE()
15446 if (N->getOpcode() == ISD::DELETED_NODE) in visitFREEZE()
15458 if (Op.getOpcode() == ISD::UNDEF) in visitFREEZE()
15462 SDValue R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops); in visitFREEZE()
15548 assert(N.getOpcode() == ISD::FMUL); in isContractableFMUL()
15666 return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue(N, 0) : FMA; in visitFADDForFMACombine()
15743 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
15761 if (N12.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
15778 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
16133 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
16139 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
16165 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
16188 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
16224 if (Fused.getOpcode() != ISD::DELETED_NODE) in visitVP_FADD()
16242 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFADD()
16280 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) in visitFADD()
16306 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) in visitFADD()
16310 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) in visitFADD()
16321 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
16331 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
16345 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && in visitFADD()
16354 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
16368 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && in visitFADD()
16377 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
16388 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
16400 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
16417 if (Fused.getOpcode() != ISD::DELETED_NODE) in visitFADD()
16462 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFSUB()
16512 N1.getOpcode() == ISD::FADD) { in visitFSUB()
16556 if (ConstOpIdx == 1 && N->getOpcode() == ISD::FDIV) in combineFMulOrFDivWithIntPow2()
16561 if (Pow2Op.getOpcode() != ISD::UINT_TO_FP && in combineFMulOrFDivWithIntPow2()
16562 (Pow2Op.getOpcode() != ISD::SINT_TO_FP || in combineFMulOrFDivWithIntPow2()
16587 N->getOpcode() == ISD::FMUL ? CurExp : (CurExp - MaxExpChange); in combineFMulOrFDivWithIntPow2()
16590 N->getOpcode() == ISD::FDIV ? CurExp : (CurExp + MaxExpChange); in combineFMulOrFDivWithIntPow2()
16635 DAG.getNode(N->getOpcode() == ISD::FMUL ? ISD::ADD : ISD::SUB, DL, in combineFMulOrFDivWithIntPow2()
16651 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFMUL()
16674 N0.getOpcode() == ISD::FMUL) { in visitFMUL()
16688 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && in visitFMUL()
16732 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && in visitFMUL()
16735 if (Select.getOpcode() != ISD::SELECT) in visitFMUL()
16743 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && in visitFMUL()
16971 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { in combineRepeatedFPDivisors()
16973 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
17020 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFDIV()
17060 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
17063 } else if (N1.getOpcode() == ISD::FP_EXTEND && in visitFDIV()
17064 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17071 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
17072 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17079 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
17083 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
17086 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
17096 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) in visitFDIV()
17133 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
17165 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) in visitFREM()
17220 if (N1.getOpcode() != ISD::FP_EXTEND && in CanCombineFCOPYSIGN_EXTEND_ROUND()
17221 N1.getOpcode() != ISD::FP_ROUND) in CanCombineFCOPYSIGN_EXTEND_ROUND()
17255 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
17256 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
17260 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
17264 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
17368 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && in foldFPToIntToFP()
17372 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && in foldFPToIntToFP()
17406 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && in visitSINT_TO_FP()
17416 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
17417 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && in visitSINT_TO_FP()
17457 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && in visitUINT_TO_FP()
17475 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
17480 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
17481 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; in FoldIntToFPToInt()
17552 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0); in visitXRINT()
17568 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
17572 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
17608 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && in visitFP_ROUND()
17634 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
17642 if (N0.getOpcode() == ISD::FP16_TO_FP && in visitFP_EXTEND()
17648 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
17703 switch (N0.getOpcode()) { in visitFTRUNC()
17754 if (N0.getOpcode() == ISD::FSUB && in visitFNEG()
17772 unsigned Opc = N->getOpcode(); in visitFMinMax()
17784 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); in visitFMinMax()
17834 if (N0.getOpcode() == ISD::FABS) in visitFABS()
17839 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) in visitFABS()
17855 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { in visitBRCOND()
17870 if (N1->getOpcode() == ISD::SETCC && N1.hasOneUse()) { in visitBRCOND()
17890 if (S0->getOpcode() == ISD::FREEZE && S0.hasOneUse() && S1C) { in visitBRCOND()
17896 if (S1->getOpcode() == ISD::FREEZE && S1.hasOneUse() && S0C) { in visitBRCOND()
17917 if (N1.getOpcode() == ISD::SETCC && in visitBRCOND()
17938 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
17939 (N.getOpcode() == ISD::TRUNCATE && in rebuildSetCC()
17941 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
17943 if (N.getOpcode() == ISD::TRUNCATE) in rebuildSetCC()
17966 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { in rebuildSetCC()
17969 if (AndOp1.getOpcode() == ISD::Constant) { in rebuildSetCC()
17985 if (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
17992 while (N.getOpcode() == ISD::XOR) { in rebuildSetCC()
18005 if (N.getOpcode() != ISD::XOR) in rebuildSetCC()
18011 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
18014 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && in rebuildSetCC()
18053 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) in visitBR_CC()
18123 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || in CombineToPreIndexedLoadStore()
18198 if (Use.getUser()->getOpcode() != ISD::ADD && in CombineToPreIndexedLoadStore()
18199 Use.getUser()->getOpcode() != ISD::SUB) { in CombineToPreIndexedLoadStore()
18295 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; in CombineToPreIndexedLoadStore()
18296 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; in CombineToPreIndexedLoadStore()
18334 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) in shouldCombineToPostInc()
18368 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { in shouldCombineToPostInc()
18476 assert((Inc.getOpcode() != ISD::TargetConstant || in SplitIndexingFromLoad()
18479 if (Inc.getOpcode() == ISD::TargetConstant) { in SplitIndexingFromLoad()
18549 if (Chain.getOpcode() == ISD::CALLSEQ_START) in getUniqueStoreFeeding()
18554 if (Chain.getOpcode() == ISD::TokenFactor) { in getUniqueStoreFeeding()
19107 if (Use->getOpcode() != ISD::BITCAST) in canMergeExpensiveCrossRegisterBankCopy()
19325 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
19333 if (User->getOpcode() != ISD::TRUNCATE) in SliceUpLoad()
19376 if (SliceInst.getOpcode() != ISD::LOAD) in SliceUpLoad()
19378 assert(SliceInst->getOpcode() == ISD::LOAD && in SliceUpLoad()
19398 if (V->getOpcode() != ISD::AND || in CheckForMaskedLoad()
19447 else if (Chain->getOpcode() == ISD::TokenFactor && in CheckForMaskedLoad()
19556 unsigned Opc = Value.getOpcode(); in ReduceLoadOpStoreWidth()
19586 if (Value.getOperand(1).getOpcode() != ISD::Constant) in ReduceLoadOpStoreWidth()
19757 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. in isMulAddWithConstProfitable()
19793 if (OtherOp->getOpcode() == ISD::ADD && in isMulAddWithConstProfitable()
19935 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
19936 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
19942 Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in mergeStoresOfConstantsOrVecElts()
20132 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
20133 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
20229 if (N->getOpcode() == ISD::TokenFactor) { in checkMergeStoreCandidatesForDependencies()
20922 if (Value.getOpcode() == ISD::TargetConstantFP) in replaceStoreOfFPConstant()
21008 if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse()) in replaceStoreOfInsertLoad()
21062 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && in visitSTORE()
21127 if ((Value.getOpcode() == ISD::ZERO_EXTEND || in visitSTORE()
21128 Value.getOpcode() == ISD::SIGN_EXTEND || in visitSTORE()
21129 Value.getOpcode() == ISD::ANY_EXTEND) && in visitSTORE()
21147 if (N->getOpcode() != ISD::DELETED_NODE) in visitSTORE()
21245 if ((Value.getOpcode() == ISD::FP_ROUND || in visitSTORE()
21246 Value.getOpcode() == ISD::TRUNCATE) && in visitSTORE()
21266 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N)) in visitSTORE()
21305 switch (Chain.getOpcode()) { in visitLIFETIME_END()
21385 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) in splitMergedValStore()
21392 if (Op1.getOpcode() != ISD::SHL) { in splitMergedValStore()
21394 if (Op1.getOpcode() != ISD::SHL) in splitMergedValStore()
21410 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
21413 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
21420 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
21423 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) in splitMergedValStore()
21460 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in mergeEltWithShuffle()
21488 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in mergeEltWithShuffle()
21525 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in mergeInsertEltWithShuffle()
21555 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && in combineInsertEltToShuffle()
21559 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || in combineInsertEltToShuffle()
21636 if (Scalar.getOpcode() == ISD::ZERO_EXTEND || in combineInsertEltToLoad()
21637 Scalar.getOpcode() == ISD::SIGN_EXTEND || in combineInsertEltToLoad()
21638 Scalar.getOpcode() == ISD::ANY_EXTEND) { in combineInsertEltToLoad()
21639 Extend = Scalar.getOpcode(); in combineInsertEltToLoad()
21649 if (Vec.getOpcode() != Extend) in combineInsertEltToLoad()
21719 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
21742 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
21755 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
21819 if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
21826 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
21832 if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) in visitINSERT_VECTOR_ELT()
21849 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
21994 if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || in scalarizeExtractedBinop()
22018 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
22101 switch (User->getOpcode()) { in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22130 if (User->getOpcode() != ISD::BUILD_VECTOR) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22199 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
22206 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22231 if (VecOp.hasOneUse() && VecOp.getOpcode() == ISD::FREEZE) { in visitEXTRACT_VECTOR_ELT()
22237 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || in visitEXTRACT_VECTOR_ELT()
22238 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
22240 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || in visitEXTRACT_VECTOR_ELT()
22244 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; in visitEXTRACT_VECTOR_ELT()
22287 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && in visitEXTRACT_VECTOR_ELT()
22299 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22326 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
22344 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22369 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
22382 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
22390 if (N->getOpcode() != ISD::DELETED_NODE) in visitEXTRACT_VECTOR_ELT()
22408 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
22443 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
22470 if (VecOp.getOpcode() == ISD::BITCAST) { in visitEXTRACT_VECTOR_ELT()
22482 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && in visitEXTRACT_VECTOR_ELT()
22548 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; in reduceBuildVecExtToExtBuildVec()
22549 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
22605 assert((Cast.getOpcode() == ISD::ANY_EXTEND || in reduceBuildVecExtToExtBuildVec()
22606 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
22644 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecTruncToBitCast()
22669 if (Op.getOpcode() == ISD::BITCAST) in reduceBuildVecTruncToBitCast()
22681 if (In.getOpcode() != ISD::TRUNCATE) in reduceBuildVecTruncToBitCast()
22686 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
22866 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); in reduceBuildVecToShuffleWithZero()
22893 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
22894 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffleWithZero()
22998 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
23173 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
23182 bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && in reduceBuildVecToShuffle()
23222 unsigned Opc = Op.getOpcode(); in convertBuildVecZextToZext()
23225 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && in convertBuildVecZextToZext()
23314 if (Op.getOpcode() != ISD::ZERO_EXTEND) in convertBuildVecZextToBuildVecWithZeros()
23420 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
23490 if (ISD::BITCAST == Op.getOpcode() && in combineConcatVectorOfScalars()
23493 else if (ISD::UNDEF == Op.getOpcode()) in combineConcatVectorOfScalars()
23545 if (Op.getOpcode() != ISD::CONCAT_VECTORS) in combineConcatVectorOfConcatVectors()
23597 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
23649 unsigned CastOpcode = N->getOperand(0).getOpcode(); in combineConcatVectorOfCasts()
23674 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || in combineConcatVectorOfCasts()
23837 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() && in visitCONCAT_VECTORS()
23849 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
23861 if (Scalar->getOpcode() == ISD::TRUNCATE && in visitCONCAT_VECTORS()
23893 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); in visitCONCAT_VECTORS()
23905 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
23917 if (ISD::UNDEF == Op.getOpcode()) in visitCONCAT_VECTORS()
23920 if (ISD::BUILD_VECTOR == Op.getOpcode()) { in visitCONCAT_VECTORS()
23976 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
24008 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
24013 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
24027 unsigned BinOpcode = BinOp.getOpcode(); in narrowInsertExtractVectorBinOp()
24076 unsigned BOpcode = BinOp.getOpcode(); in narrowExtractedVectorBinOp()
24158 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) in narrowExtractedVectorBinOp()
24260 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
24418 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { in visitEXTRACT_SUBVECTOR()
24428 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
24435 if (V.getOpcode() == ISD::BITCAST && in visitEXTRACT_SUBVECTOR()
24486 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
24529 if (V.getOpcode() == ISD::BUILD_VECTOR) { in visitEXTRACT_SUBVECTOR()
24561 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
24603 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
24604 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || in foldShuffleOfConcatUndefs()
24768 if (S.getOpcode() == ISD::BUILD_VECTOR) { in combineShuffleOfScalars()
24770 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
25023 unsigned Opcode = N0.getOpcode(); in combineTruncationShuffle()
25180 if (Op0.getOpcode() != ISD::BITCAST) in combineShuffleOfBitcast()
25184 (!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || in combineShuffleOfBitcast()
25324 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceShuffleOfInsert()
25429 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { in visitVECTOR_SHUFFLE()
25439 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); in visitVECTOR_SHUFFLE()
25449 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
25452 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) in visitVECTOR_SHUFFLE()
25459 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() && in visitVECTOR_SHUFFLE()
25461 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || in visitVECTOR_SHUFFLE()
25462 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) { in visitVECTOR_SHUFFLE()
25479 if (V->getOpcode() == ISD::BITCAST) { in visitVECTOR_SHUFFLE()
25486 if (V->getOpcode() == ISD::BUILD_VECTOR) { in visitVECTOR_SHUFFLE()
25541 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25544 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25553 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && in visitVECTOR_SHUFFLE()
25582 assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); in visitVECTOR_SHUFFLE()
25627 if (N1.getOpcode() == ISD::CONCAT_VECTORS) in visitVECTOR_SHUFFLE()
25630 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { in visitVECTOR_SHUFFLE()
25701 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && in visitVECTOR_SHUFFLE()
25706 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { in visitVECTOR_SHUFFLE()
25880 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25881 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
25898 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25899 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25913 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25940 unsigned SrcOpcode = N0.getOpcode(); in visitVECTOR_SHUFFLE()
25943 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { in visitVECTOR_SHUFFLE()
25954 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
25955 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
25956 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
25957 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { in visitVECTOR_SHUFFLE()
26039 unsigned Opcode = Scalar.getOpcode(); in visitSCALAR_TO_VECTOR()
26056 if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitSCALAR_TO_VECTOR()
26135 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26155 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
26163 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && in visitINSERT_SUBVECTOR()
26164 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26177 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
26194 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26203 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26212 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && in visitINSERT_SUBVECTOR()
26213 N1.getOpcode() == ISD::BITCAST) { in visitINSERT_SUBVECTOR()
26250 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
26265 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
26286 if (N0->getOpcode() == ISD::FP16_TO_FP) in visitFP_TO_FP16()
26293 auto Op = N->getOpcode(); in visitFP16_TO_FP()
26300 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { in visitFP16_TO_FP()
26314 if (N0->getOpcode() == ISD::BF16_TO_FP) in visitFP_TO_BF16()
26328 unsigned Opcode = N->getOpcode(); in visitVECREDUCE()
26354 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitVECREDUCE()
26381 if (N->getOpcode() == ISD::VP_GATHER) in visitVPOp()
26385 if (N->getOpcode() == ISD::VP_SCATTER) in visitVPOp()
26389 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD) in visitVPOp()
26393 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE) in visitVPOp()
26401 if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) in visitVPOp()
26403 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) in visitVPOp()
26409 switch (N->getOpcode()) { in visitVPOp()
26421 if (ISD::isVPBinaryOp(N->getOpcode())) in visitVPOp()
26433 if (ISD::isVPReduction(N->getOpcode())) in visitVPOp()
26535 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); in XformToShuffleWithZero()
26547 if (RHS.getOpcode() != ISD::BUILD_VECTOR) in XformToShuffleWithZero()
26625 unsigned Opcode = N->getOpcode(); in scalarizeBinOpOfSplats()
26638 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && in scalarizeBinOpOfSplats()
26639 N1.getOpcode() == ISD::SPLAT_VECTOR; in scalarizeBinOpOfSplats()
26654 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && in scalarizeBinOpOfSplats()
26673 unsigned Opcode = N->getOpcode(); in SimplifyVCastOp()
26682 (N0.getOpcode() == ISD::SPLAT_VECTOR || in SimplifyVCastOp()
26708 unsigned Opcode = N->getOpcode(); in SimplifyVBinOp()
26738 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
26747 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { in SimplifyVBinOp()
26760 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && in SimplifyVBinOp()
26761 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && in SimplifyVBinOp()
26781 return Concat.getOpcode() == ISD::CONCAT_VECTORS && in SimplifyVBinOp()
26818 assert(N0.getOpcode() == ISD::SETCC && in SimplifySelect()
26830 if (SCC.getOpcode() == ISD::SELECT_CC) { in SimplifySelect()
26858 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
26865 if (TheSelect->getOpcode() == ISD::SELECT_CC) { in SimplifySelectOps()
26872 if (Cmp.getOpcode() == ISD::SETCC) { in SimplifySelectOps()
26892 if (LHS.getOpcode() != RHS.getOpcode() || in SimplifySelectOps()
26900 if (LHS.getOpcode() == ISD::LOAD) { in SimplifySelectOps()
26929 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
26930 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || in SimplifySelectOps()
26931 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), in SimplifySelectOps()
26958 if (TheSelect->getOpcode() == ISD::SELECT) { in SimplifySelectOps()
27120 unsigned BinOpc = N1.getOpcode(); in foldSelectOfBinops()
27121 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc) || in foldSelectOfBinops()
27172 bool IsFabs = N->getOpcode() == ISD::FABS; in foldSignChangeInBitcast()
27175 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) in foldSignChangeInBitcast()
27303 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && in SimplifySelectCC()
27393 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
27394 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && in SimplifySelectCC()
27400 if ((Count.getOpcode() == ISD::CTLZ || in SimplifySelectCC()
27401 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && in SimplifySelectCC()
27539 switch (V.getOpcode()) { in takeInexpensiveLog2()
27596 if (Op.getOpcode() == ISD::SHL) { in takeInexpensiveLog2()
27607 if ((Op.getOpcode() == ISD::SELECT || Op.getOpcode() == ISD::VSELECT) && in takeInexpensiveLog2()
27618 if ((Op.getOpcode() == ISD::UMIN || Op.getOpcode() == ISD::UMAX) && in takeInexpensiveLog2()
27628 return DAG.getNode(Op.getOpcode(), DL, VT, LogX, LogY); in takeInexpensiveLog2()
28011 switch (C.getOpcode()) { in GatherAllAliases()
28074 if (Chain.getOpcode() == ISD::TokenFactor) { in GatherAllAliases()