Lines Matching refs:IsAnd
598 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
5937 SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, in foldLogicOfSetCCs() argument
5969 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero; in foldLogicOfSetCCs()
5971 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
5973 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero; in foldLogicOfSetCCs()
5975 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
5988 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1; in foldLogicOfSetCCs()
5990 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; in foldLogicOfSetCCs()
5992 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1; in foldLogicOfSetCCs()
5994 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; in foldLogicOfSetCCs()
6009 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && in foldLogicOfSetCCs()
6026 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) { in foldLogicOfSetCCs()
6035 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) { in foldLogicOfSetCCs()
6069 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT) in foldLogicOfSetCCs()