238 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {  in addPhysRegDataDeps()  argument
239   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);  in addPhysRegDataDeps()
249   bool ImplicitPseudoDef = (OperIdx >= DefMIDesc.getNumOperands() &&  in addPhysRegDataDeps()
280         Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,  in addPhysRegDataDeps()
285       ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep);  in addPhysRegDataDeps()
294 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {  in addPhysRegDeps()  argument
296   MachineOperand &MO = MI->getOperand(OperIdx);  in addPhysRegDeps()
324               SchedModel.computeOutputLatency(MI, OperIdx, DefInstr));  in addPhysRegDeps()
326         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);  in addPhysRegDeps()
338       Uses.insert(PhysRegSUOper(SU, OperIdx, Unit));  in addPhysRegDeps()
342     addPhysRegDataDeps(SU, OperIdx);  in addPhysRegDeps()
372       Defs.insert(PhysRegSUOper(SU, OperIdx, Unit));  in addPhysRegDeps()
403 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {  in addVRegDefDeps()  argument
405   MachineOperand &MO = MI->getOperand(OperIdx);  in addVRegDefDeps()
423            llvm::drop_begin(MI->operands(), OperIdx + 1))  in addVRegDefDeps()
454         Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,  in addVRegDefDeps()
456         ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep);  in addVRegDefDeps()
498       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
522 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {  in addVRegUseDeps()  argument
526   const MachineOperand &MO = MI->getOperand(OperIdx);  in addVRegUseDeps()
532   CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));  in addVRegUseDeps()