314       SUnit *DefSU = I->SU;  in addPhysRegDeps()  local
315       if (DefSU == &ExitSU)  in addPhysRegDeps()
317       MachineInstr *DefInstr = DefSU->getInstr();  in addPhysRegDeps()
319       if (DefSU != SU &&  in addPhysRegDeps()
326         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);  in addPhysRegDeps()
327         DefSU->addPred(Dep);  in addPhysRegDeps()
488     SUnit *DefSU = V2SU.SU;  in addVRegDefDeps()  local
494     if (DefSU == SU)  in addVRegDefDeps()
498       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
499     DefSU->addPred(Dep);  in addVRegDefDeps()
509       CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));  in addVRegDefDeps()