Lines Matching refs:PhysReg
403 MCRegister PhysReg; in tryAssign() local
404 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
410 PhysReg = *I; in tryAssign()
413 if (!PhysReg.isValid()) in tryAssign()
414 return PhysReg; in tryAssign()
441 uint8_t Cost = RegCosts[PhysReg]; in tryAssign()
445 return PhysReg; in tryAssign()
447 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign()
450 return CheapReg ? CheapReg : PhysReg; in tryAssign()
484 MCRegister PhysReg, in evictInterference() argument
491 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference()
496 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in evictInterference()
524 bool RegAllocEvictionAdvisor::isUnusedCalleeSavedReg(MCRegister PhysReg) const { in isUnusedCalleeSavedReg()
525 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
529 return !Matrix->isPhysRegUsed(PhysReg); in isUnusedCalleeSavedReg()
560 MCRegister PhysReg) const { in canAllocatePhysReg()
561 if (RegCosts[PhysReg] >= CostPerUseLimit) in canAllocatePhysReg()
565 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { in canAllocatePhysReg()
567 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in canAllocatePhysReg()
568 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in canAllocatePhysReg()
767 if (Cand.PhysReg) { in growRegion()
1096 RAGreedy::calculateRegionSplitCostAroundReg(MCPhysReg PhysReg, in calculateRegionSplitCostAroundReg() argument
1107 if (CandIndex == BestCand || !GlobalCand[CandIndex].PhysReg) in calculateRegionSplitCostAroundReg()
1124 Cand.reset(IntfCache, PhysReg); in calculateRegionSplitCostAroundReg()
1129 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCostAroundReg()
1132 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) in calculateRegionSplitCostAroundReg()
1140 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCostAroundReg()
1179 for (MCPhysReg PhysReg : Order) { in calculateRegionSplitCost() local
1180 assert(PhysReg); in calculateRegionSplitCost()
1181 if (IgnoreCSR && EvictAdvisor->isUnusedCalleeSavedReg(PhysReg)) in calculateRegionSplitCost()
1184 calculateRegionSplitCostAroundReg(PhysReg, Order, BestCost, NumCands, in calculateRegionSplitCost()
1208 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in " in doRegionSplit()
1217 assert(!Cand.PhysReg && "Compact region has no physreg"); in doRegionSplit()
1491 void RAGreedy::calcGapWeights(MCRegister PhysReg, in calcGapWeights() argument
1507 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcGapWeights()
1542 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcGapWeights()
1659 for (MCPhysReg PhysReg : Order) { in tryLocalSplit() local
1660 assert(PhysReg); in tryLocalSplit()
1663 calcGapWeights(PhysReg, GapWeight); in tryLocalSplit()
1666 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) in tryLocalSplit()
1685 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore] in tryLocalSplit()
1812 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit() local
1813 if (PhysReg || !NewVRegs.empty()) in trySplit()
1814 return PhysReg; in trySplit()
1827 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit() local
1828 if (PhysReg || !NewVRegs.empty()) in trySplit()
1829 return PhysReg; in trySplit()
1853 MCRegister PhysReg, in assignedRegPartiallyOverlaps() argument
1856 if (PhysReg == AssignedReg) in assignedRegPartiallyOverlaps()
1858 return TRI.regsOverlap(PhysReg, AssignedReg); in assignedRegPartiallyOverlaps()
1870 MCRegister PhysReg, const LiveInterval &VirtReg, in mayRecolorAllInterferences() argument
1874 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in mayRecolorAllInterferences()
1899 !assignedRegPartiallyOverlaps(*TRI, *VRM, PhysReg, *Intf)) && in mayRecolorAllInterferences()
1991 for (MCRegister PhysReg : Order) { in tryLastChanceRecoloring() local
1992 assert(PhysReg.isValid()); in tryLastChanceRecoloring()
1994 << printReg(PhysReg, TRI) << '\n'); in tryLastChanceRecoloring()
1999 if (Matrix->checkInterference(VirtReg, PhysReg) > in tryLastChanceRecoloring()
2009 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates, in tryLastChanceRecoloring()
2035 Matrix->assign(VirtReg, PhysReg); in tryLastChanceRecoloring()
2049 return PhysReg; in tryLastChanceRecoloring()
2053 << printReg(PhysReg, TRI) << '\n'); in tryLastChanceRecoloring()
2077 MCRegister PhysReg; in tryLastChanceRecoloring() local
2078 std::tie(LI, PhysReg) = RecolorStack[I]; in tryLastChanceRecoloring()
2086 MCRegister PhysReg; in tryLastChanceRecoloring() local
2087 std::tie(LI, PhysReg) = RecolorStack[I]; in tryLastChanceRecoloring()
2089 Matrix->assign(*LI, PhysReg); in tryLastChanceRecoloring()
2116 MCRegister PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, in tryRecoloringCandidates() local
2122 if (PhysReg == ~0u || (!PhysReg && !LI->empty())) in tryRecoloringCandidates()
2125 if (!PhysReg) { in tryRecoloringCandidates()
2132 << " succeeded with: " << printReg(PhysReg, TRI) << '\n'); in tryRecoloringCandidates()
2134 Matrix->assign(*LI, PhysReg); in tryRecoloringCandidates()
2177 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg, in tryAssignCSRFirstTime() argument
2184 return PhysReg; in tryAssignCSRFirstTime()
2201 return PhysReg; in tryAssignCSRFirstTime()
2207 return PhysReg; in tryAssignCSRFirstTime()
2268 MCRegister PhysReg) { in getBrokenHintFreq() argument
2271 if (Info.PhysReg != PhysReg) in getBrokenHintFreq()
2293 MCRegister PhysReg = VRM->getPhys(Reg); in tryHintRecoloring() local
2300 << '(' << printReg(PhysReg, TRI) << ")\n"); in tryHintRecoloring()
2322 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) || in tryHintRecoloring()
2323 Matrix->checkInterference(LI, PhysReg))) in tryHintRecoloring()
2334 if (CurrPhys != PhysReg) { in tryHintRecoloring()
2337 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg); in tryHintRecoloring()
2351 Matrix->assign(LI, PhysReg); in tryHintRecoloring()
2419 if (MCRegister PhysReg = in selectOrSplitImpl() local
2425 EvictAdvisor->isUnusedCalleeSavedReg(PhysReg) && NewVRegs.empty()) { in selectOrSplitImpl()
2426 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, in selectOrSplitImpl()
2433 return PhysReg; in selectOrSplitImpl()
2447 if (Register PhysReg = in selectOrSplitImpl() local
2456 if (Hint && Hint != PhysReg) in selectOrSplitImpl()
2458 return PhysReg; in selectOrSplitImpl()
2476 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters); in selectOrSplitImpl() local
2477 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore)) in selectOrSplitImpl()
2478 return PhysReg; in selectOrSplitImpl()