402                                const SmallVirtRegSet &FixedRegisters) {  in tryAssign()  argument
426                                                  FixedRegisters)) {  in tryAssign()
449   MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters);  in tryAssign()
583                               const SmallVirtRegSet &FixedRegisters) {  in tryEvict()  argument
588       VirtReg, Order, CostPerUseLimit, FixedRegisters);  in tryEvict()
1802                             const SmallVirtRegSet &FixedRegisters) {  in trySplit()  argument
1871     SmallLISet &RecoloringCandidates, const SmallVirtRegSet &FixedRegisters) {  in mayRecolorAllInterferences()  argument
1902           FixedRegisters.count(Intf->reg())) {  in mayRecolorAllInterferences()
1959                                            SmallVirtRegSet &FixedRegisters,  in tryLastChanceRecoloring()  argument
1987   assert(!FixedRegisters.count(VirtReg.reg()));  in tryLastChanceRecoloring()
1988   FixedRegisters.insert(VirtReg.reg());  in tryLastChanceRecoloring()
2010                                     FixedRegisters)) {  in tryLastChanceRecoloring()
2040     SmallVirtRegSet SaveFixedRegisters(FixedRegisters);  in tryLastChanceRecoloring()
2042                                 FixedRegisters, RecolorStack, Depth)) {  in tryLastChanceRecoloring()
2056     FixedRegisters = SaveFixedRegisters;  in tryLastChanceRecoloring()
2110                                        SmallVirtRegSet &FixedRegisters,  in tryRecoloringCandidates()  argument
2116     MCRegister PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters,  in tryRecoloringCandidates()
2135     FixedRegisters.insert(LI->reg());  in tryRecoloringCandidates()
2148   SmallVirtRegSet FixedRegisters;  in selectOrSplit()  local
2151       selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters, RecolorStack);  in selectOrSplit()
2412                                        SmallVirtRegSet &FixedRegisters,  in selectOrSplitImpl()  argument
2420           tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {  in selectOrSplitImpl()
2449                      FixedRegisters)) {  in selectOrSplitImpl()
2476     Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);  in selectOrSplitImpl()
2484     return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,  in selectOrSplitImpl()