262   ExtraInfo->LRE_DidCloneVirtReg(New, Old);  in LRE_DidCloneVirtReg()
292   auto Stage = ExtraInfo->getOrInitStage(Reg);  in enqueue()
295     ExtraInfo->setStage(Reg, Stage);  in enqueue()
489   unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg());  in evictInterference()
513     assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||  in evictInterference()
516     ExtraInfo->setCascade(Intf->reg(), Cascade);  in evictInterference()
1032     if (ExtraInfo->getOrInitStage(Reg.reg()) != RS_New)  in splitAroundRegion()
1038       ExtraInfo->setStage(Reg, RS_Spill);  in splitAroundRegion()
1049         ExtraInfo->setStage(Reg, RS_Split2);  in splitAroundRegion()
1244   if (ExtraInfo->getStage(VirtReg) >= RS_Split2)  in trySplitAroundHintReg()
1323     if (ExtraInfo->getOrInitStage(LI.reg()) == RS_New && IntvMap[I] == 0)  in tryBlockSplit()
1324       ExtraInfo->setStage(LI, RS_Spill);  in tryBlockSplit()
1478   ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);  in tryInstructionSplit()
1647   bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2;  in tryLocalSplit()
1783         ExtraInfo->setStage(LIS->getInterval(LREdit.get(I)), RS_Split2);  in tryLocalSplit()
1804   if (ExtraInfo->getStage(VirtReg) >= RS_Spill)  in trySplit()
1826   if (ExtraInfo->getStage(VirtReg) < RS_Split2) {  in trySplit()
1897       if (((ExtraInfo->getStage(*Intf) == RS_Done &&  in mayRecolorAllInterferences()
1970   assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&  in tryLastChanceRecoloring()
2179   if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {  in tryAssignCSRFirstTime()
2191   if (ExtraInfo->getStage(VirtReg) < RS_Split) {  in tryAssignCSRFirstTime()
2439   LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);  in selectOrSplitImpl()
2441                     << ExtraInfo->getCascade(VirtReg.reg()) << '\n');  in selectOrSplitImpl()
2467     ExtraInfo->setStage(VirtReg, RS_Split);  in selectOrSplitImpl()
2491       ExtraInfo->getStage(VirtReg) < RS_Memory) {  in selectOrSplitImpl()
2496     ExtraInfo->setStage(VirtReg, RS_Memory);  in selectOrSplitImpl()
2504     ExtraInfo->setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);  in selectOrSplitImpl()
2751   ExtraInfo.emplace();  in runOnMachineFunction()