Lines Matching refs:Unit

276     for (MCRegUnit Unit : TRI->regunits(PhysReg))  in markRegUsedInInstr()  local
277 UsedInInstr.insert(Unit); in markRegUsedInInstr()
291 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isRegUsedInInstr() local
292 if (UsedInInstr.count(Unit)) in isRegUsedInInstr()
294 if (LookAtPhysRegUses && PhysRegUses.count(Unit)) in isRegUsedInInstr()
303 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markPhysRegUsedInInstr() local
304 PhysRegUses.insert(Unit); in markPhysRegUsedInInstr()
309 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in unmarkRegUsedInInstr() local
310 UsedInInstr.erase(Unit); in unmarkRegUsedInInstr()
425 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in setPhysRegState() local
426 RegUnitStates[Unit] = NewState; in setPhysRegState()
430 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isPhysRegFree() local
431 if (RegUnitStates[Unit] != regFree) in isPhysRegFree()
703 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in displacePhysReg() local
704 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg()
719 RegUnitStates[Unit] = regFree; in displacePhysReg()
757 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcSpillCost() local
758 switch (unsigned VirtReg = RegUnitStates[Unit]) { in calcSpillCost()
1194 for (unsigned Unit = 1, UnitE = TRI->getNumRegUnits(); Unit != UnitE; in dumpState() local
1195 ++Unit) { in dumpState()
1196 switch (unsigned VirtReg = RegUnitStates[Unit]) { in dumpState()
1200 dbgs() << " " << printRegUnit(Unit, TRI) << "[P]"; in dumpState()
1205 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg); in dumpState()
1216 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1229 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in dumpState() local
1230 assert(RegUnitStates[Unit] == VirtReg && "inverse map valid"); in dumpState()