Lines Matching refs:PhysReg
206 MCPhysReg PhysReg = 0; ///< Currently held here. member
271 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
272 bool isPhysRegFree(MCPhysReg PhysReg) const;
275 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
276 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markRegUsedInInstr()
281 bool isClobberedByRegMasks(MCPhysReg PhysReg) const { in isClobberedByRegMasks()
282 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) { in isClobberedByRegMasks()
283 return MachineOperand::clobbersPhysReg(Mask, PhysReg); in isClobberedByRegMasks()
288 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
289 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg)) in isRegUsedInInstr()
291 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isRegUsedInInstr()
302 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr() argument
303 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markPhysRegUsedInInstr()
308 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr() argument
309 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in unmarkRegUsedInInstr()
361 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
362 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
363 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
364 void freePhysReg(MCPhysReg PhysReg);
366 unsigned calcSpillCost(MCPhysReg PhysReg) const;
376 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
393 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
403 MCPhysReg PhysReg);
424 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState() argument
425 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in setPhysRegState()
429 bool RegAllocFast::isPhysRegFree(MCPhysReg PhysReg) const { in isPhysRegFree()
430 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isPhysRegFree()
600 MCPhysReg PhysReg) { in reload() argument
602 << printReg(PhysReg, TRI) << '\n'); in reload()
605 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); in reload()
645 MCPhysReg Reg = P.PhysReg; in reloadAtBegin()
658 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
659 if (PhysReg == 0) in reloadAtBegin()
662 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in reloadAtBegin()
669 if (PrologLiveIns.count(PhysReg)) { in reloadAtBegin()
673 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
675 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
700 bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) { in displacePhysReg() argument
703 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in displacePhysReg()
710 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
712 setPhysRegState(LRI->PhysReg, regFree); in displacePhysReg()
713 LRI->PhysReg = 0; in displacePhysReg()
729 void RegAllocFast::freePhysReg(MCPhysReg PhysReg) { in freePhysReg() argument
730 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
732 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in freePhysReg()
739 setPhysRegState(PhysReg, regFree); in freePhysReg()
745 setPhysRegState(LRI->PhysReg, regFree); in freePhysReg()
746 LRI->PhysReg = 0; in freePhysReg()
756 unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { in calcSpillCost()
757 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcSpillCost()
763 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
813 MCPhysReg PhysReg) { in assignVirtToPhysReg() argument
816 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
817 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
818 assert(PhysReg != 0 && "Trying to assign no register"); in assignVirtToPhysReg()
819 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
820 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
822 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
867 assert(LR.PhysReg == 0); in allocVirtReg()
912 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() local
913 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' '); in allocVirtReg()
914 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) { in allocVirtReg()
919 unsigned Cost = calcSpillCost(PhysReg); in allocVirtReg()
923 assignVirtToPhysReg(MI, LR, PhysReg); in allocVirtReg()
927 if (PhysReg == Hint0 || PhysReg == Hint1) in allocVirtReg()
931 BestReg = PhysReg; in allocVirtReg()
945 LR.PhysReg = 0; in allocVirtReg()
961 MCPhysReg PhysReg; in allocVirtRegUndef() local
962 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in allocVirtRegUndef()
963 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
968 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
973 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
976 MO.setReg(PhysReg); in allocVirtRegUndef()
989 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg()
994 LRI->PhysReg = 0; in defineLiveThroughVirtReg()
998 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to " in defineLiveThroughVirtReg()
1002 .addReg(LRI->PhysReg, llvm::RegState::Kill); in defineLiveThroughVirtReg()
1038 if (LRI->PhysReg == 0) { in defineVirtReg()
1050 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) && in defineVirtReg()
1054 << printReg(LRI->PhysReg, TRI) << '\n'); in defineVirtReg()
1057 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg() local
1065 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
1075 TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI, in defineVirtReg()
1078 Succ->addLiveIn(PhysReg); in defineVirtReg()
1089 BundleVirtRegsMap[VirtReg] = PhysReg; in defineVirtReg()
1091 markRegUsedInInstr(PhysReg); in defineVirtReg()
1092 return setPhysReg(MI, MO, PhysReg); in defineVirtReg()
1119 if (LRI->PhysReg == 0) { in useVirtReg()
1145 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
1147 markRegUsedInInstr(LRI->PhysReg); in useVirtReg()
1148 return setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
1154 MCPhysReg PhysReg) { in setPhysReg() argument
1156 MO.setReg(PhysReg); in setPhysReg()
1162 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1173 MI.addRegisterKilled(PhysReg, TRI, true); in setPhysReg()
1182 MI.addRegisterDead(PhysReg, TRI, true); in setPhysReg()
1184 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
1216 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1226 MCPhysReg PhysReg = LR.PhysReg; in dumpState() local
1227 if (PhysReg != 0) { in dumpState()
1228 assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg"); in dumpState()
1229 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in dumpState()
1505 MCPhysReg PhysReg = LR.PhysReg; in allocateInstruction() local
1506 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg)) in allocateInstruction()
1507 displacePhysReg(MI, PhysReg); in allocateInstruction()
1637 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in handleDebugValue()
1640 setPhysReg(MI, *RegMO, LRI->PhysReg); in handleDebugValue()
1683 setPhysRegState(LiveReg.PhysReg, regPreAssigned); in allocateBasicBlock()