Lines Matching refs:Def
258 RegSubRegPair Def, RewriteMapTy &RewriteMap);
413 const MachineInstr *Def = nullptr; member in __anon139b6b7f0111::ValueTracker
469 Def = MRI.getVRegDef(Reg); in ValueTracker()
1176 RegSubRegPair Def, in getNewSource() argument
1179 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1287 RegSubRegPair Def, RewriteMapTy &RewriteMap) { in rewriteSource() argument
1288 assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers"); in rewriteSource()
1291 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource()
1294 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1302 if (Def.SubReg) { in rewriteSource()
1303 NewCopy->getOperand(0).setSubReg(Def.SubReg); in rewriteSource()
1310 MRI->replaceRegWith(Def.Reg, NewVReg); in rewriteSource()
1341 RegSubRegPair Def; in optimizeUncoalescableCopy() local
1343 while (CpyRewriter.getNextRewritableSource(Src, Def)) { in optimizeUncoalescableCopy()
1346 if (Def.Reg.isPhysical()) in optimizeUncoalescableCopy()
1351 if (!findNextSource(Def, RewriteMap)) in optimizeUncoalescableCopy()
1354 RewritePairs.push_back(Def); in optimizeUncoalescableCopy()
1358 for (const RegSubRegPair &Def : RewritePairs) { in optimizeUncoalescableCopy() local
1360 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap); in optimizeUncoalescableCopy()
1732 const auto &Def = NAPhysToVirtMIs.find(Reg); in runOnMachineFunction() local
1733 if (Def != NAPhysToVirtMIs.end()) { in runOnMachineFunction()
1738 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1744 Register Def = RegMI.first; in runOnMachineFunction() local
1745 if (MachineOperand::clobbersPhysReg(RegMask, Def)) { in runOnMachineFunction()
1748 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1883 assert(Def->isCopy() && "Invalid definition"); in getNextSourceFromCopy()
1888 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 && in getNextSourceFromCopy()
1890 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed"); in getNextSourceFromCopy()
1892 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1897 const MachineOperand &Src = Def->getOperand(1); in getNextSourceFromCopy()
1904 assert(Def->isBitcast() && "Invalid definition"); in getNextSourceFromBitcast()
1907 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects()) in getNextSourceFromBitcast()
1911 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1913 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1919 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast()
1922 const MachineOperand &MO = Def->getOperand(OpIdx); in getNextSourceFromBitcast()
1937 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1947 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
1954 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1957 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1980 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1998 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
2001 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2014 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
2030 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
2051 assert((Def->isExtractSubreg() || in getNextSourceFromExtractSubreg()
2052 Def->isExtractSubregLike()) && "Invalid definition"); in getNextSourceFromExtractSubreg()
2067 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg)) in getNextSourceFromExtractSubreg()
2080 assert(Def->isSubregToReg() && "Invalid definition"); in getNextSourceFromSubregToReg()
2088 if (DefSubReg != Def->getOperand(3).getImm()) in getNextSourceFromSubregToReg()
2092 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
2095 return ValueTrackerResult(Def->getOperand(2).getReg(), in getNextSourceFromSubregToReg()
2096 Def->getOperand(3).getImm()); in getNextSourceFromSubregToReg()
2101 assert(Def->isPHI() && "Invalid definition"); in getNextSourceFromPHI()
2106 if (Def->getOperand(0).getSubReg() != DefSubReg) in getNextSourceFromPHI()
2110 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { in getNextSourceFromPHI()
2111 const MachineOperand &MO = Def->getOperand(i); in getNextSourceFromPHI()
2124 assert(Def && "This method needs a valid definition"); in getNextSourceImpl()
2126 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2127 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2128 Def->getDesc().isVariadic())) || in getNextSourceImpl()
2129 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
2131 if (Def->isCopy()) in getNextSourceImpl()
2133 if (Def->isBitcast()) in getNextSourceImpl()
2139 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
2141 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
2143 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) in getNextSourceImpl()
2145 if (Def->isSubregToReg()) in getNextSourceImpl()
2147 if (Def->isPHI()) in getNextSourceImpl()
2155 if (!Def) in getNextSource()
2168 Res.setInst(Def); in getNextSource()
2175 Def = DI->getParent(); in getNextSource()
2179 Def = nullptr; in getNextSource()
2187 Def = nullptr; in getNextSource()