Lines Matching refs:Reg
57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
59 VRegInfo[Reg].first = RC; in setRegClass()
62 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
64 VRegInfo[Reg].first = &RegBank; in setRegBank()
68 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
79 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
84 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass() argument
85 if (Reg.isPhysical()) in constrainRegClass()
87 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
91 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
94 const LLT RegTy = getType(Reg); in constrainRegAttrs()
101 const auto &RegCB = getRegClassOrRegBank(Reg); in constrainRegAttrs()
103 setRegClassOrRegBank(Reg, ConstrainingRegCB); in constrainRegAttrs()
109 *this, Reg, cast<const TargetRegisterClass *>(RegCB), in constrainRegAttrs()
116 setType(Reg, ConstrainingRegTy); in constrainRegAttrs()
121 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass() argument
123 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
132 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
141 setRegClass(Reg, NewRC); in recomputeRegClass()
146 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister() local
147 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
148 RegAllocHints.grow(Reg); in createIncompleteVirtualRegister()
149 insertVRegByName(Name, Reg); in createIncompleteVirtualRegister()
150 return Reg; in createIncompleteVirtualRegister()
164 Register Reg = createIncompleteVirtualRegister(Name); in createVirtualRegister() local
165 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
166 noteNewVirtualRegister(Reg); in createVirtualRegister()
167 return Reg; in createVirtualRegister()
172 Register Reg = createIncompleteVirtualRegister(Name); in cloneVirtualRegister() local
173 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
174 setType(Reg, getType(VReg)); in cloneVirtualRegister()
175 noteCloneVirtualRegister(Reg, VReg); in cloneVirtualRegister()
176 return Reg; in cloneVirtualRegister()
187 Register Reg = createIncompleteVirtualRegister(Name); in createGenericVirtualRegister() local
189 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); in createGenericVirtualRegister()
190 setType(Reg, Ty); in createGenericVirtualRegister()
191 noteNewVirtualRegister(Reg); in createGenericVirtualRegister()
192 return Reg; in createGenericVirtualRegister()
201 Register Reg = Register::index2VirtReg(i); in clearVirtRegs() local
202 if (!VRegInfo[Reg].second) in clearVirtRegs()
204 verifyUseList(Reg); in clearVirtRegs()
206 << printReg(Reg, getTargetRegisterInfo()) << "...\n"; in clearVirtRegs()
207 for (MachineInstr &MI : reg_instructions(Reg)) in clearVirtRegs()
217 void MachineRegisterInfo::verifyUseList(Register Reg) const { in verifyUseList()
220 for (MachineOperand &M : reg_operands(Reg)) { in verifyUseList()
224 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
233 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
239 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
244 if (MO->getReg() != Reg) { in verifyUseList()
245 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
276 MO->Contents.Reg.Prev = MO; in addRegOperandToUseList()
277 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
284 MachineOperand *Last = Head->Contents.Reg.Prev; in addRegOperandToUseList()
287 Head->Contents.Reg.Prev = MO; in addRegOperandToUseList()
288 MO->Contents.Reg.Prev = Last; in addRegOperandToUseList()
294 MO->Contents.Reg.Next = Head; in addRegOperandToUseList()
298 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
299 Last->Contents.Reg.Next = MO; in addRegOperandToUseList()
311 MachineOperand *Next = MO->Contents.Reg.Next; in removeRegOperandFromUseList()
312 MachineOperand *Prev = MO->Contents.Reg.Prev; in removeRegOperandFromUseList()
318 Prev->Contents.Reg.Next = Next; in removeRegOperandFromUseList()
320 (Next ? Next : Head)->Contents.Reg.Prev = Prev; in removeRegOperandFromUseList()
322 MO->Contents.Reg.Prev = nullptr; in removeRegOperandFromUseList()
323 MO->Contents.Reg.Next = nullptr; in removeRegOperandFromUseList()
353 MachineOperand *Prev = Src->Contents.Reg.Prev; in moveOperands()
354 MachineOperand *Next = Src->Contents.Reg.Next; in moveOperands()
363 Prev->Contents.Reg.Next = Dst; in moveOperands()
367 (Next ? Next : Head)->Contents.Reg.Prev = Dst; in moveOperands()
398 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { in getVRegDef()
400 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
409 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { in getUniqueVRegDef()
410 if (def_empty(Reg)) return nullptr; in getUniqueVRegDef()
411 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
425 bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg, in hasAtMostUserInstrs() argument
427 return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(), in hasAtMostUserInstrs()
435 void MachineRegisterInfo::clearKillFlags(Register Reg) const { in clearKillFlags()
436 for (MachineOperand &MO : use_operands(Reg)) in clearKillFlags()
440 bool MachineRegisterInfo::isLiveIn(Register Reg) const { in isLiveIn()
442 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn()
497 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { in getMaxLaneMaskForVReg()
499 assert(Reg.isVirtual()); in getMaxLaneMaskForVReg()
500 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg()
505 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { in dumpUses()
506 for (MachineInstr &I : use_instructions(Reg)) in dumpUses()
536 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { in markUsesInDebugValueAsUndef()
539 for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) { in markUsesInDebugValueAsUndef()
540 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg)) in markUsesInDebugValueAsUndef()
602 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { in disableCalleeSavedRegister() argument
605 assert(Reg && (Reg < TRI->getNumRegs()) && in disableCalleeSavedRegister()
621 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in disableCalleeSavedRegister()
655 MCRegister Reg) const { in isArgumentRegister()
656 return getTargetRegisterInfo()->isArgumentRegister(MF, Reg); in isArgumentRegister()
660 MCRegister Reg) const { in isFixedRegister()
661 return getTargetRegisterInfo()->isFixedRegister(MF, Reg); in isFixedRegister()
665 MCRegister Reg) const { in isGeneralPurposeRegister()
666 return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg); in isGeneralPurposeRegister()