159       Register Reg = MO.getReg();  in finalizeBundle()  local
160       if (!Reg)  in finalizeBundle()
163       if (LocalDefSet.count(Reg)) {  in finalizeBundle()
167           KilledDefSet.insert(Reg);  in finalizeBundle()
169         if (ExternUseSet.insert(Reg).second) {  in finalizeBundle()
170           ExternUses.push_back(Reg);  in finalizeBundle()
172             UndefUseSet.insert(Reg);  in finalizeBundle()
176           KilledUseSet.insert(Reg);  in finalizeBundle()
182       Register Reg = MO.getReg();  in finalizeBundle()  local
183       if (!Reg)  in finalizeBundle()
186       if (LocalDefSet.insert(Reg).second) {  in finalizeBundle()
187         LocalDefs.push_back(Reg);  in finalizeBundle()
189           DeadDefSet.insert(Reg);  in finalizeBundle()
193         KilledDefSet.erase(Reg);  in finalizeBundle()
196           DeadDefSet.erase(Reg);  in finalizeBundle()
199       if (!MO.isDead() && Reg.isPhysical()) {  in finalizeBundle()
200         for (MCPhysReg SubReg : TRI->subregs(Reg)) {  in finalizeBundle()
211   for (Register Reg : LocalDefs) {  in finalizeBundle()  local
212     if (Added.insert(Reg).second) {  in finalizeBundle()
214       bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);  in finalizeBundle()
215       MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |  in finalizeBundle()
220   for (Register Reg : ExternUses) {  in finalizeBundle()  local
221     bool isKill = KilledUseSet.count(Reg);  in finalizeBundle()
222     bool isUndef = UndefUseSet.count(Reg);  in finalizeBundle()
223     MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |  in finalizeBundle()
279     MachineInstr &MI, Register Reg,  in AnalyzeVirtRegInBundle()  argument
284     if (!MO.isReg() || MO.getReg() != Reg)  in AnalyzeVirtRegInBundle()
309 llvm::AnalyzeVirtRegLanesInBundle(const MachineInstr &MI, Register Reg,  in AnalyzeVirtRegLanesInBundle()  argument
317     if (!MO.isReg() || MO.getReg() != Reg)  in AnalyzeVirtRegLanesInBundle()
322       UseMask |= MRI.getMaxLaneMaskForVReg(Reg);  in AnalyzeVirtRegLanesInBundle()
336 PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg,  in AnalyzePhysRegInBundle()  argument
341   assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!");  in AnalyzePhysRegInBundle()
345     if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {  in AnalyzePhysRegInBundle()
357     if (!TRI->regsOverlap(MOReg, Reg))  in AnalyzePhysRegInBundle()
360     bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);  in AnalyzePhysRegInBundle()