168     if (MO.isReg())  in removeRegOperandsFromUseLists()
174     if (MO.isReg())  in addRegOperandsToUseLists()
223   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
225     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {  in addOperand()
263   if (NewMO->isReg()) {  in addOperand()
298     if (Operands[i].isReg())  in removeOperand()
303   if (MRI && Operands[OpNo].isReg())  in removeOperand()
641     if (!MO.isReg()) {  in isIdenticalTo()
761     if (MO.isReg() && MO.isImplicit())  in getNumExplicitOperands()
775     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in getNumExplicitDefs()
915   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
964   if (!MO.isReg() || MO.getReg() != Reg)  in getRegClassConstraintEffectForVRegImpl()
975   assert(MO.isReg() &&  in getRegClassConstraintEffect()
1005     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)  in hasRegisterImplicitUseOperand()
1018     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
1042     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
1072     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
1164       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)  in findTiedOperandIdx()
1178       while (!getOperand(CurUseIdx).isReg())  in findTiedOperandIdx()
1227     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1239       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1245       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1495     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1505     if (!MO.isReg() || MO.isUse())  in allImplicitDefsAreDead()
1519     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())  in copyImplicitOps()
1529     if (!Operand.isReg() || Operand.isDef())  in hasComplexRegisterTies()
1543   if (!Op.isReg())  in getTypeToPrint()
1583     if (!MO.isReg() || MO.isDef())  in dumprImpl()
1638     if (MO.isReg() && MO.isTied() && !MO.isDef())  in print()
1648     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in print()
1936     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
1997     if (!MO.isReg() || !MO.isUse() || !MO.isKill())  in clearRegisterKills()
2015     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
2059     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)  in clearRegisterDeads()
2067     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)  in setRegisterDefReadUndef()
2081       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&  in addRegisterDefined()
2099     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()
2123     if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())  in getHashValue()
2181     if (DebugOp.isReg())  in BuildMI()
2196     if (DebugOp.isReg())  in BuildMI()
2276       if (Op.isReg() && Op.getReg() == SpillReg)  in buildDbgValueForSpill()
2318   if (!MI.getOperand(0).isReg())  in collectDebugValues()
2335   if (!getOperand(0).isReg())  in changeDebugValuesDefReg()
2498     if (MO.isReg() && MO.isTied()) {  in insert()
2536   if (!getOperand(OpId).isReg())  in mayFoldInlineAsmRegOp()