427                                  const MachineOperand &MODef, Register Def);
642     const MachineInstr &MI, const MachineOperand &MODef, Register Def) {  in hasOverlappingMultipleDef()  argument
644     if ((&MIDef != &MODef) && MIDef.isReg() &&  in hasOverlappingMultipleDef()
971     MachineOperand &MODef = MI.getOperand(OpIdx);  in propagateDefs()  local
973     if (!MODef.isReg() || MODef.isUse())  in propagateDefs()
977     if (MODef.isTied() || MODef.isUndef() || MODef.isImplicit())  in propagateDefs()
980     if (!MODef.getReg())  in propagateDefs()
984     if (!MODef.isRenamable())  in propagateDefs()
988         MI, MODef.getReg().asMCReg(), *TRI, *TII, UseCopyInstr);  in propagateDefs()
997     if (MODef.getReg() != Src)  in propagateDefs()
1003     if (hasImplicitOverlap(MI, MODef))  in propagateDefs()
1006     if (hasOverlappingMultipleDef(MI, MODef, Def))  in propagateDefs()
1009     LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MODef.getReg(), TRI)  in propagateDefs()
1013     MODef.setReg(Def);  in propagateDefs()
1014     MODef.setIsRenamable(CopyOperands->Destination->isRenamable());  in propagateDefs()