Lines Matching refs:DefInstr
154 MachineInstr *DefInstr = nullptr; in getOperandDef() local
157 DefInstr = MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef()
159 if (DefInstr && DefInstr->isPHI()) in getOperandDef()
160 DefInstr = nullptr; in getOperandDef()
161 return DefInstr; in getOperandDef()
231 MachineInstr *DefInstr = InsInstrs[II->second]; in getDepth() local
232 assert(DefInstr && in getDepth()
235 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth()
237 LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx, in getDepth()
240 MachineInstr *DefInstr = getOperandDef(MO); in getDepth() local
241 if (DefInstr && (TII->getMachineCombinerTraceStrategy() != in getDepth()
243 DefInstr->getParent() == &MBB)) { in getDepth()
244 DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth; in getDepth()
245 if (!isTransientMI(DefInstr)) in getDepth()
247 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()