Lines Matching refs:buildUndef

274       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in buildLCMMergePieces()
319         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in buildLCMMergePieces()
1203       Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);  in narrowScalar()
1214       DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));  in narrowScalar()
1873     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);  in widenScalarMergeValues()
4361       MIRBuilder.buildUndef(DstReg);  in fewerElementsVectorExtractInsertVectorElt()
4759           SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0));  in fewerElementsVectorShuffle()
4778       Output = MIRBuilder.buildUndef(NarrowTy).getReg(0);  in fewerElementsVectorShuffle()
4783                          ? MIRBuilder.buildUndef(NarrowTy).getReg(0)  in fewerElementsVectorShuffle()
5300       Elts.push_back(MIRBuilder.buildUndef(MoreTy.getScalarType()));  in moreElementsVector()
5376   auto Undef = MIRBuilder.buildUndef(SrcTy);  in equalizeVectorShuffleLengths()
7214         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);  in lowerShuffleVector()