Lines Matching refs:InL
4947 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant() local
4949 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); in narrowScalarShiftByConstant()
4952 MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {InL, InH}); in narrowScalarShiftByConstant()
4967 Hi = MIRBuilder.buildShl(NVT, InL, in narrowScalarShiftByConstant()
4971 Hi = InL; in narrowScalarShiftByConstant()
4973 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); in narrowScalarShiftByConstant()
4977 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); in narrowScalarShiftByConstant()
4993 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); in narrowScalarShiftByConstant()
5016 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); in narrowScalarShiftByConstant()
5070 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift() local
5072 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); in narrowScalarShift()
5085 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
5087 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); in narrowScalarShift()
5093 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. in narrowScalarShift()
5108 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); in narrowScalarShift()
5124 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); in narrowScalarShift()