Lines Matching refs:getOrCreateVReg
304 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateBinaryOp()
305 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateBinaryOp()
306 Register Res = getOrCreateVReg(U); in translateBinaryOp()
319 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateUnaryOp()
320 Register Res = getOrCreateVReg(U); in translateUnaryOp()
337 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateCompare()
338 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateCompare()
339 Register Res = getOrCreateVReg(U); in translateCompare()
347 Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); in translateCompare()
350 Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); in translateCompare()
865 Register SwitchOpReg = getOrCreateVReg(SValue); in emitJumpTableHeader()
886 auto Cst = getOrCreateVReg( in emitJumpTableHeader()
902 Register CondLHS = getOrCreateVReg(*CB.CmpLHS); in emitSwitchCase()
931 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
946 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS); in emitSwitchCase()
948 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
1090 Register SwitchOpReg = getOrCreateVReg(*B.SValue); in emitBitTestHeader()
1338 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr()
1373 Register Base = getOrCreateVReg(*LI.getPointerOperand()); in translateLoad()
1423 Register Base = getOrCreateVReg(*SI.getPointerOperand()); in translateStore()
1516 Register Tst = getOrCreateVReg(*U.getOperand(0)); in translateSelect()
1534 Register Src = getOrCreateVReg(V); in translateCopy()
1568 Register Op = getOrCreateVReg(*U.getOperand(0)); in translateCast()
1569 Register Res = getOrCreateVReg(U); in translateCast()
1577 Register BaseReg = getOrCreateVReg(Op0); in translateGetElementPtr()
1642 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr()
1675 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0), in translateGetElementPtr()
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1696 Register SrcReg = getOrCreateVReg(**AI); in translateMemFunc()
1803 {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))}); in translateOverflowIntrinsic()
1810 Register Dst = getOrCreateVReg(CI); in translateFixedPointIntrinsic()
1811 Register Src0 = getOrCreateVReg(*CI.getOperand(0)); in translateFixedPointIntrinsic()
1812 Register Src1 = getOrCreateVReg(*CI.getOperand(1)); in translateFixedPointIntrinsic()
1944 VRegs.push_back(getOrCreateVReg(*Arg)); in translateSimpleIntrinsic()
1946 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
1988 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(0))); in translateConstrainedFPIntrinsic()
1990 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(1))); in translateConstrainedFPIntrinsic()
1992 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(2))); in translateConstrainedFPIntrinsic()
1994 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
2117 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) in translateKnownIntrinsic()
2184 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2185 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2186 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2187 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2)); in translateKnownIntrinsic()
2206 MIRBuilder.buildFPExt(getOrCreateVReg(CI), in translateKnownIntrinsic()
2207 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2212 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), in translateKnownIntrinsic()
2213 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2219 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2233 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2245 getStackGuard(getOrCreateVReg(CI), MIRBuilder); in translateKnownIntrinsic()
2255 GuardVal = getOrCreateVReg(*CI.getArgOperand(0)); // The guard's value. in translateKnownIntrinsic()
2262 GuardVal, getOrCreateVReg(*Slot), in translateKnownIntrinsic()
2270 MIRBuilder.buildInstr(TargetOpcode::G_STACKSAVE, {getOrCreateVReg(CI)}, {}); in translateKnownIntrinsic()
2275 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2287 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2288 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2305 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2306 getOrCreateVReg(*CI.getArgOperand(0))); in translateKnownIntrinsic()
2319 .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {}) in translateKnownIntrinsic()
2327 .addUse(getOrCreateVReg(*CI.getArgOperand(1))); in translateKnownIntrinsic()
2361 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2362 Register ScalarSrc = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2363 Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2422 {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2423 {getOrCreateVReg(*CI.getArgOperand(0))}, Flags) in translateKnownIntrinsic()
2433 .buildInstr(TargetOpcode::G_IS_FPCLASS, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2434 {getOrCreateVReg(*FpValue)}) in translateKnownIntrinsic()
2442 {getOrCreateVReg(*FPEnv)}); in translateKnownIntrinsic()
2452 { getOrCreateVReg(*FPState) }); in translateKnownIntrinsic()
2469 MIRBuilder.buildPrefetch(getOrCreateVReg(*Addr), RW, Locality, CacheType, in translateKnownIntrinsic()
2535 [&]() { return getOrCreateVReg(*CB.getCalledOperand()); }); in translateCallBase()
2874 Register Res = getOrCreateVReg(AI); in translateAlloca()
2885 Register NumElts = getOrCreateVReg(*AI.getArraySize()); in translateAlloca()
2898 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty))); in translateAlloca()
2915 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment); in translateAlloca()
2927 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, in translateVAArg()
2928 {getOrCreateVReg(*U.getOperand(0)), in translateVAArg()
2962 Register Res = getOrCreateVReg(U); in translateInsertElement()
2963 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateInsertElement()
2964 Register Elt = getOrCreateVReg(*U.getOperand(1)); in translateInsertElement()
2965 Register Idx = getOrCreateVReg(*U.getOperand(2)); in translateInsertElement()
2977 Register Res = getOrCreateVReg(U); in translateExtractElement()
2978 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateExtractElement()
2986 Idx = getOrCreateVReg(*NewIdxCI); in translateExtractElement()
2990 Idx = getOrCreateVReg(*U.getOperand(1)); in translateExtractElement()
3008 .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)}, in translateShuffleVector()
3009 {getOrCreateVReg(*U.getOperand(0)), in translateShuffleVector()
3010 getOrCreateVReg(*U.getOperand(1))}) in translateShuffleVector()
3038 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicCmpXchg()
3039 Register Cmp = getOrCreateVReg(*I.getCompareOperand()); in translateAtomicCmpXchg()
3040 Register NewVal = getOrCreateVReg(*I.getNewValOperand()); in translateAtomicCmpXchg()
3057 Register Res = getOrCreateVReg(I); in translateAtomicRMW()
3058 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicRMW()
3059 Register Val = getOrCreateVReg(*I.getValOperand()); in translateAtomicRMW()
3261 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), in translateDbgDeclareRecord()
3325 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3335 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3352 Ops.push_back(getOrCreateVReg(*CV->getOperand(i))); in translate()
3553 Register GuardPtr = getOrCreateVReg(*IRGuard); in emitSPDescriptorParent()