168         Info.OrigRet.Regs[0] = ReturnHintAlignReg;  in lowerCall()
273     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),  in splitToValueTypes()
280   assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");  in splitToValueTypes()
286     SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,  in splitToValueTypes()
344                               ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,  in buildCopyFromRegs()  argument
351     assert(OrigRegs[0] == Regs[0]);  in buildCopyFromRegs()
356       Regs.size() == 1) {  in buildCopyFromRegs()
357     B.buildBitcast(OrigRegs[0], Regs[0]);  in buildCopyFromRegs()
367       OrigRegs.size() == 1 && Regs.size() == 1) {  in buildCopyFromRegs()
368     Register SrcReg = Regs[0];  in buildCopyFromRegs()
396     unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();  in buildCopyFromRegs()
398       B.buildMergeValues(OrigRegs[0], Regs);  in buildCopyFromRegs()
400       auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs);  in buildCopyFromRegs()
409     SmallVector<Register> CastRegs(Regs.begin(), Regs.end());  in buildCopyFromRegs()
417         Regs.size() == 1) {  in buildCopyFromRegs()
420       CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);  in buildCopyFromRegs()
455       for (Register Reg : Regs)  in buildCopyFromRegs()
459     B.buildBuildVector(OrigRegs[0], Regs);  in buildCopyFromRegs()
470           B.buildMergeLikeInstr(RealDstEltTy, Regs.take_front(PartsPerElt));  in buildCopyFromRegs()
474       Regs = Regs.drop_front(PartsPerElt);  in buildCopyFromRegs()
485     if (NumElts == Regs.size())  in buildCopyFromRegs()
486       BuildVec = B.buildBuildVector(BVType, Regs).getReg(0);  in buildCopyFromRegs()
490       assert(NumElts > Regs.size());  in buildCopyFromRegs()
491       LLT SrcEltTy = MRI.getType(Regs[0]);  in buildCopyFromRegs()
502       BVRegs.reserve(Regs.size() * EltPerReg);  in buildCopyFromRegs()
503       for (Register R : Regs) {  in buildCopyFromRegs()
750     Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());  in handleAssignments()
755       Args[i].Regs.resize(NumParts);  in handleAssignments()
761         Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);  in handleAssignments()
770       buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,  in handleAssignments()
776       Register ArgReg = Args[i].Regs[Part];  in handleAssignments()
799         assert(Args[i].Regs.size() == 1 &&  in handleAssignments()
807           MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);  in handleAssignments()
833           Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],  in handleAssignments()
863       buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,  in handleAssignments()
1048     if (OutInfo.Regs.size() > 1) {  in parametersInCSRMatch()
1057     MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);  in parametersInCSRMatch()