Lines Matching refs:IVSigned
2815 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPOuterLoop() local
2839 RT.emitForNext(*this, S.getBeginLoc(), IVSize, IVSigned, LoopArgs.IL, in EmitOMPOuterLoop()
2880 [&S, &LoopArgs, LoopExit, &CodeGenLoop, IVSize, IVSigned, &CodeGenOrdered, in EmitOMPOuterLoop()
2893 [IVSize, IVSigned, Loc, &CodeGenOrdered](CodeGenFunction &CGF) { in EmitOMPOuterLoop()
2894 CodeGenOrdered(CGF, Loc, IVSize, IVSigned); in EmitOMPOuterLoop()
2987 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPForOuterLoop() local
2997 IVSigned, Ordered, DipatchRTInputValues); in EmitOMPForOuterLoop()
3000 IVSize, IVSigned, Ordered, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, in EmitOMPForOuterLoop()
3008 const bool IVSigned) { in EmitOMPForOuterLoop() argument
3011 IVSigned); in EmitOMPForOuterLoop()
3027 const unsigned IVSize, const bool IVSigned) {} in emitEmptyOrdered() argument
3043 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeOuterLoop() local
3046 IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, in EmitOMPDistributeOuterLoop()
3375 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPWorksharingLoop() local
3408 [IVSize, IVSigned, Ordered, IL, LB, UB, ST, StaticChunkedOne, Chunk, in EmitOMPWorksharingLoop()
3417 IVSize, IVSigned, Ordered, IL.getAddress(CGF), in EmitOMPWorksharingLoop()
5696 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeLoop() local
5713 IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(*this), in EmitOMPDistributeLoop()