245     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,  in initFeatureMap()  argument
251     Features["64bit"] = true;  in initFeatureMap()
254     Features["32bit"] = true;  in initFeatureMap()
272     return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);  in initFeatureMap()
290   return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures);  in initFeatureMap()
333 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,  in handleTargetFeatures()  argument
336   auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, Features);  in handleTargetFeatures()
355   FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");  in handleTargetFeatures()
357   if (llvm::is_contained(Features, "+experimental"))  in handleTargetFeatures()
391                                  std::vector<std::string> &Features) {  in handleFullArchString()  argument
392   Features.push_back("__RISCV_TargetAttrNeedOverride");  in handleFullArchString()
397     Features.push_back("+" + FullArchStr.str());  in handleFullArchString()
403     Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());  in handleFullArchString()
407 ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {  in parseTargetAttr()
409   if (Features == "default")  in parseTargetAttr()
412   Features.split(AttrFeatures, ";");  in parseTargetAttr()
421       Ret.Features.clear();  in parseTargetAttr()
438             Ret.Features.push_back(Ext.front() + TargetFeature);  in parseTargetAttr()
440             Ret.Features.push_back(Ext.str());  in parseTargetAttr()
444         handleFullArchString(AttrString, Ret.Features);  in parseTargetAttr()
456           Ret.Features.clear();  in parseTargetAttr()
457           handleFullArchString(MarchFromCPU, Ret.Features);  in parseTargetAttr()