Lines Matching refs:temp
301 uint32_t temp; in xhci_reset_command_queue_locked() local
305 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
306 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
308 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
317 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
320 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
327 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
328 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
366 uint32_t temp; in xhci_start_controller() local
386 temp = XREAD4(sc, oper, XHCI_USBSTS); in xhci_start_controller()
389 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
464 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_start_controller()
465 temp |= XHCI_IMAN_INTR_ENA; in xhci_start_controller()
466 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
487 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_start_controller()
488 if (!temp) in xhci_start_controller()
491 if (temp) { in xhci_start_controller()
511 uint32_t temp; in xhci_halt_controller() local
526 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_halt_controller()
527 if (temp) in xhci_halt_controller()
531 if (!temp) { in xhci_halt_controller()
541 uint32_t temp = 0; in xhci_reset_controller() local
551 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | in xhci_reset_controller()
553 if (!temp) in xhci_reset_controller()
557 if (temp) { in xhci_reset_controller()
568 uint32_t temp; in xhci_init() local
607 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); in xhci_init()
609 DPRINTF("HCS0 = 0x%08x\n", temp); in xhci_init()
612 if (XHCI_HCS0_CSZ(temp)) { in xhci_init()
619 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && in xhci_init()
628 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); in xhci_init()
631 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); in xhci_init()
640 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); in xhci_init()
647 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); in xhci_init()
649 DPRINTF("HCS2=0x%08x\n", temp); in xhci_init()
652 sc->sc_ist = XHCI_HCS2_IST(temp); in xhci_init()
655 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); in xhci_init()
666 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); in xhci_init()
670 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); in xhci_init()
673 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + in xhci_init()
674 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; in xhci_init()
914 uint32_t temp; in xhci_check_transfer() local
925 temp = le32toh(trb->dwTrb2); in xhci_check_transfer()
927 remainder = XHCI_TRB_2_REM_GET(temp); in xhci_check_transfer()
928 status = XHCI_TRB_2_ERROR_GET(temp); in xhci_check_transfer()
930 temp = le32toh(trb->dwTrb3); in xhci_check_transfer()
931 epno = XHCI_TRB_3_EP_GET(temp); in xhci_check_transfer()
932 index = XHCI_TRB_3_SLOT_GET(temp); in xhci_check_transfer()
996 temp = le32toh(td->td_trb[i].dwTrb2); in xhci_check_transfer()
997 remainder += XHCI_TRB_2_BYTES_GET(temp); in xhci_check_transfer()
1092 uint32_t temp; in xhci_interrupt_poll() local
1113 temp = le32toh(phwr->hwr_events[i].dwTrb3); in xhci_interrupt_poll()
1115 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; in xhci_interrupt_poll()
1120 event = XHCI_TRB_3_TYPE_GET(temp); in xhci_interrupt_poll()
1180 uint32_t temp; in xhci_do_command() local
1212 temp = trb->dwTrb3; in xhci_do_command()
1215 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1217 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1219 temp &= ~htole32(XHCI_TRB_3_TC_BIT); in xhci_do_command()
1221 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1234 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1238 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1242 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1278 temp = le32toh(trb->dwTrb3); in xhci_do_command()
1285 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && in xhci_do_command()
1286 (temp & XHCI_TRB_3_BSR_BIT) == 0) { in xhci_do_command()
1300 temp = le32toh(sc->sc_cmd_result[0]); in xhci_do_command()
1301 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) in xhci_do_command()
1318 uint32_t temp;
1324 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1326 trb.dwTrb3 = htole32(temp);
1336 uint32_t temp; in xhci_cmd_enable_slot() local
1349 temp = le32toh(trb.dwTrb3); in xhci_cmd_enable_slot()
1351 *pslot = XHCI_TRB_3_SLOT_GET(temp); in xhci_cmd_enable_slot()
1361 uint32_t temp; in xhci_cmd_disable_slot() local
1367 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | in xhci_cmd_disable_slot()
1370 trb.dwTrb3 = htole32(temp); in xhci_cmd_disable_slot()
1380 uint32_t temp; in xhci_cmd_set_address() local
1386 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | in xhci_cmd_set_address()
1390 temp |= XHCI_TRB_3_BSR_BIT; in xhci_cmd_set_address()
1392 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_address()
1406 uint32_t temp; in xhci_set_address() local
1480 temp = le32toh(sc->sc_cmd_result[0]); in xhci_set_address()
1482 XHCI_TRB_2_ERROR_GET(temp) == in xhci_set_address()
1500 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); in xhci_set_address()
1501 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); in xhci_set_address()
1529 uint32_t temp; in xhci_cmd_configure_ep() local
1535 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | in xhci_cmd_configure_ep()
1541 temp |= XHCI_TRB_3_DCEP_BIT; in xhci_cmd_configure_ep()
1544 trb.dwTrb3 = htole32(temp); in xhci_cmd_configure_ep()
1554 uint32_t temp; in xhci_cmd_evaluate_ctx() local
1560 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | in xhci_cmd_evaluate_ctx()
1562 trb.dwTrb3 = htole32(temp); in xhci_cmd_evaluate_ctx()
1572 uint32_t temp; in xhci_cmd_reset_ep() local
1578 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | in xhci_cmd_reset_ep()
1583 temp |= XHCI_TRB_3_PRSV_BIT; in xhci_cmd_reset_ep()
1585 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_ep()
1595 uint32_t temp; in xhci_cmd_set_tr_dequeue_ptr() local
1601 temp = XHCI_TRB_2_STREAM_SET(stream_id); in xhci_cmd_set_tr_dequeue_ptr()
1602 trb.dwTrb2 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1604 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | in xhci_cmd_set_tr_dequeue_ptr()
1607 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1617 uint32_t temp; in xhci_cmd_stop_ep() local
1623 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | in xhci_cmd_stop_ep()
1628 temp |= XHCI_TRB_3_SUSP_EP_BIT; in xhci_cmd_stop_ep()
1630 trb.dwTrb3 = htole32(temp); in xhci_cmd_stop_ep()
1639 uint32_t temp; in xhci_cmd_reset_dev() local
1645 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | in xhci_cmd_reset_dev()
1648 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_dev()
1660 uint32_t temp; in xhci_interrupt() local
1672 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_interrupt()
1675 if (temp & XHCI_IMAN_INTR_PEND) in xhci_interrupt()
1676 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
1732 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) in xhci_setup_generic_chain_sub() argument
1750 shortpkt_old = temp->shortpkt; in xhci_setup_generic_chain_sub()
1751 len_old = temp->len; in xhci_setup_generic_chain_sub()
1757 td = temp->td; in xhci_setup_generic_chain_sub()
1758 td_next = td_first = temp->td_next; in xhci_setup_generic_chain_sub()
1761 if (temp->len == 0) { in xhci_setup_generic_chain_sub()
1762 if (temp->shortpkt) in xhci_setup_generic_chain_sub()
1767 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1771 average = temp->average; in xhci_setup_generic_chain_sub()
1773 if (temp->len < average) { in xhci_setup_generic_chain_sub()
1774 if (temp->len % temp->max_packet_size) { in xhci_setup_generic_chain_sub()
1775 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1777 average = temp->len; in xhci_setup_generic_chain_sub()
1794 temp->len -= average; in xhci_setup_generic_chain_sub()
1806 temp->len -= average; in xhci_setup_generic_chain_sub()
1812 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { in xhci_setup_generic_chain_sub()
1820 usbd_copy_out(temp->pc, temp->offset + buf_offset, in xhci_setup_generic_chain_sub()
1857 usbd_get_page(temp->pc, temp->offset + in xhci_setup_generic_chain_sub()
1873 temp->max_packet_size); in xhci_setup_generic_chain_sub()
1891 switch (temp->trb_type) { in xhci_setup_generic_chain_sub()
1894 XHCI_TRB_3_TBC_SET(temp->tbc) | in xhci_setup_generic_chain_sub()
1895 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); in xhci_setup_generic_chain_sub()
1898 } else if (temp->do_isoc_sync != 0) { in xhci_setup_generic_chain_sub()
1899 temp->do_isoc_sync = 0; in xhci_setup_generic_chain_sub()
1902 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); in xhci_setup_generic_chain_sub()
1908 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1914 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1924 temp->trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain_sub()
1929 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1935 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1998 if (temp->last_frame) { in xhci_setup_generic_chain_sub()
2006 temp->shortpkt = shortpkt_old; in xhci_setup_generic_chain_sub()
2007 temp->len = len_old; in xhci_setup_generic_chain_sub()
2015 if (temp->step_td != 0) { in xhci_setup_generic_chain_sub()
2029 temp->td = td; in xhci_setup_generic_chain_sub()
2030 temp->td_next = td_next; in xhci_setup_generic_chain_sub()
2036 struct xhci_std_temp temp; in xhci_setup_generic_chain() local
2042 temp.do_isoc_sync = 0; in xhci_setup_generic_chain()
2043 temp.step_td = 0; in xhci_setup_generic_chain()
2044 temp.tbc = 0; in xhci_setup_generic_chain()
2045 temp.tlbpc = 0; in xhci_setup_generic_chain()
2046 temp.average = xfer->max_hc_frame_size; in xhci_setup_generic_chain()
2047 temp.max_packet_size = xfer->max_packet_size; in xhci_setup_generic_chain()
2048 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); in xhci_setup_generic_chain()
2049 temp.pc = NULL; in xhci_setup_generic_chain()
2050 temp.last_frame = 0; in xhci_setup_generic_chain()
2051 temp.offset = 0; in xhci_setup_generic_chain()
2052 temp.multishort = xfer->flags_int.isochronous_xfr || in xhci_setup_generic_chain()
2062 temp.td = NULL; in xhci_setup_generic_chain()
2063 temp.td_next = td; in xhci_setup_generic_chain()
2086 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); in xhci_setup_generic_chain()
2088 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); in xhci_setup_generic_chain()
2093 temp.isoc_delta = 8; /* 1ms */ in xhci_setup_generic_chain()
2097 temp.isoc_delta = 1U << shift; in xhci_setup_generic_chain()
2102 if (temp.sc->sc_ist & 8) in xhci_setup_generic_chain()
2103 y = (temp.sc->sc_ist & 7) << 3; in xhci_setup_generic_chain()
2105 y = (temp.sc->sc_ist & 7); in xhci_setup_generic_chain()
2111 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); in xhci_setup_generic_chain()
2130 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { in xhci_setup_generic_chain()
2132 temp.do_isoc_sync = 1; in xhci_setup_generic_chain()
2134 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); in xhci_setup_generic_chain()
2138 temp.trb_type = XHCI_TRB_TYPE_ISOCH; in xhci_setup_generic_chain()
2144 temp.len = xfer->frlengths[0]; in xhci_setup_generic_chain()
2145 temp.pc = xfer->frbuffers + 0; in xhci_setup_generic_chain()
2146 temp.shortpkt = temp.len ? 1 : 0; in xhci_setup_generic_chain()
2147 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; in xhci_setup_generic_chain()
2148 temp.direction = 0; in xhci_setup_generic_chain()
2154 temp.last_frame = 1; in xhci_setup_generic_chain()
2157 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2161 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2162 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2163 temp.trb_type = xfer->flags_int.control_did_data ? in xhci_setup_generic_chain()
2168 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2169 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2170 temp.trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain()
2175 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2177 temp.direction = UE_GET_DIR(xfer->endpointno); in xhci_setup_generic_chain()
2183 temp.len = xfer->frlengths[x]; in xhci_setup_generic_chain()
2184 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && in xhci_setup_generic_chain()
2185 x != 0 && temp.multishort == 0); in xhci_setup_generic_chain()
2193 temp.last_frame = 1; in xhci_setup_generic_chain()
2195 temp.last_frame = 1; in xhci_setup_generic_chain()
2198 if (temp.len == 0) { in xhci_setup_generic_chain()
2201 temp.shortpkt = 0; in xhci_setup_generic_chain()
2203 temp.tbc = 0; in xhci_setup_generic_chain()
2204 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2214 temp.shortpkt = 1; in xhci_setup_generic_chain()
2218 if (temp.len > xfer->max_frame_size) in xhci_setup_generic_chain()
2219 temp.len = xfer->max_frame_size; in xhci_setup_generic_chain()
2222 tdpc = howmany(temp.len, xfer->max_packet_size); in xhci_setup_generic_chain()
2224 temp.tbc = howmany(tdpc, mult) - 1; in xhci_setup_generic_chain()
2225 temp.tlbpc = (tdpc % mult); in xhci_setup_generic_chain()
2227 if (temp.tlbpc == 0) in xhci_setup_generic_chain()
2228 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2230 temp.tlbpc--; in xhci_setup_generic_chain()
2234 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; in xhci_setup_generic_chain()
2237 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2240 temp.offset += xfer->frlengths[x - 1]; in xhci_setup_generic_chain()
2241 temp.isoc_frame += temp.isoc_delta; in xhci_setup_generic_chain()
2244 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2256 if (xhcictlstep || temp.sc->sc_ctlstep) { in xhci_setup_generic_chain()
2263 temp.step_td = (xfer->nframes != 0); in xhci_setup_generic_chain()
2265 temp.step_td = 0; in xhci_setup_generic_chain()
2267 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; in xhci_setup_generic_chain()
2268 temp.len = 0; in xhci_setup_generic_chain()
2269 temp.pc = NULL; in xhci_setup_generic_chain()
2270 temp.shortpkt = 0; in xhci_setup_generic_chain()
2271 temp.last_frame = 1; in xhci_setup_generic_chain()
2272 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; in xhci_setup_generic_chain()
2274 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2277 td = temp.td; in xhci_setup_generic_chain()
2309 uint32_t temp; in xhci_configure_mask() local
2350 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); in xhci_configure_mask()
2351 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); in xhci_configure_mask()
2352 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); in xhci_configure_mask()
2353 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); in xhci_configure_mask()
2370 uint32_t temp; in xhci_configure_endpoint() local
2407 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2414 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2435 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2438 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2444 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); in xhci_configure_endpoint()
2455 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); in xhci_configure_endpoint()
2457 temp = in xhci_configure_endpoint()
2469 temp |= XHCI_EPCTX_1_CERR_SET(3); in xhci_configure_endpoint()
2473 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2476 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); in xhci_configure_endpoint()
2479 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); in xhci_configure_endpoint()
2482 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); in xhci_configure_endpoint()
2488 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2490 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); in xhci_configure_endpoint()
2496 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | in xhci_configure_endpoint()
2501 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); in xhci_configure_endpoint()
2504 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); in xhci_configure_endpoint()
2508 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); in xhci_configure_endpoint()
2531 uint64_t temp; in xhci_configure_endpoint_by_xfer() local
2537 temp = pepext->physaddr + in xhci_configure_endpoint_by_xfer()
2543 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); in xhci_configure_endpoint_by_xfer()
2569 uint32_t temp; in xhci_configure_device() local
2616 temp = XHCI_SCTX_0_ROUTE_SET(route) | in xhci_configure_device()
2622 temp |= XHCI_SCTX_0_SPEED_SET(2); in xhci_configure_device()
2627 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2631 temp |= XHCI_SCTX_0_SPEED_SET(3); in xhci_configure_device()
2635 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2639 temp |= XHCI_SCTX_0_SPEED_SET(1); in xhci_configure_device()
2644 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2648 temp |= XHCI_SCTX_0_SPEED_SET(4); in xhci_configure_device()
2657 temp |= XHCI_SCTX_0_HUB_SET(1); in xhci_configure_device()
2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); in xhci_configure_device()
2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); in xhci_configure_device()
2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET( in xhci_configure_device()
2668 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); in xhci_configure_device()
2670 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); in xhci_configure_device()
2673 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( in xhci_configure_device()
2684 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( in xhci_configure_device()
2686 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( in xhci_configure_device()
2694 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); in xhci_configure_device()
2700 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | in xhci_configure_device()
2703 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); in xhci_configure_device()
3307 sc->sc_hub_desc.temp[0] = sc->sc_conf; in xhci_roothub_exec()
3358 sc->sc_hub_desc.temp, in xhci_roothub_exec()
3359 sizeof(sc->sc_hub_desc.temp), in xhci_roothub_exec()
3370 sc->sc_hub_desc.temp[0] = 0; in xhci_roothub_exec()
3514 memset(sc->sc_hub_desc.temp, 0, 16); in xhci_roothub_exec()
3796 uint32_t temp; in xhci_get_endpoint_state() local
3806 temp = xhci_ctx_get_le32(sc, &pdev->ctx_ep[epno - 1].dwEpCtx0); in xhci_get_endpoint_state()
3808 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); in xhci_get_endpoint_state()
4115 uint8_t temp; in xhci_device_init() local
4129 err = xhci_cmd_enable_slot(sc, &temp); in xhci_device_init()
4136 if (temp > sc->sc_noslot) { in xhci_device_init()
4141 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { in xhci_device_init()
4142 DPRINTF("slot %u already allocated.\n", temp); in xhci_device_init()
4149 udev->controller_slot_id = temp; in xhci_device_init()
4153 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); in xhci_device_init()
4157 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; in xhci_device_init()