55 #define	UART_CTRL		0x08		/* Control Register */  macro
183 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_param()
184 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |  in uart_mvebu_param()
222 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_param()
236 	uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &  in uart_mvebu_init()
339 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_attach()
346 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_attach()
369 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_flush()
373 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);  in uart_mvebu_bus_flush()
378 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);  in uart_mvebu_bus_flush()
389 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_flush()
415 		ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ioctl()
420 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_ioctl()
448 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ipend()
453 		uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);  in uart_mvebu_bus_ipend()
564 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_transmit()
565 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_transmit()
577 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);  in uart_mvebu_bus_transmit()
596 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_grab()
598 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_grab()
612 	ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;  in uart_mvebu_bus_ungrab()
613 	uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);  in uart_mvebu_bus_ungrab()