51 #define	GETREG(bas, reg)	\  argument
52     bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
53 #define	SETREG(bas, reg, value)	\  argument
54     bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
61 static int	msm_probe(struct uart_bas *bas);
62 static void	msm_init(struct uart_bas *bas, int, int, int, int);
63 static void	msm_term(struct uart_bas *bas);
64 static void	msm_putc(struct uart_bas *bas, int);
65 static int	msm_rxready(struct uart_bas *bas);
66 static int	msm_getc(struct uart_bas *bas, struct mtx *mtx);
71 msm_uart_param(struct uart_bas *bas, int baudrate, int databits,  in msm_uart_param()  argument
123 	uart_setreg(bas, UART_DM_MR2, ulcon);  in msm_uart_param()
124 	uart_barrier(bas);  in msm_uart_param()
139 msm_probe(struct uart_bas *bas)  in msm_probe()  argument
142 	bas->regiowidth = 4;  in msm_probe()
148 msm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,  in msm_init()  argument
152 	if (bas->rclk == 0)  in msm_init()
153 		bas->rclk = DEF_CLK;  in msm_init()
155 	KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));  in msm_init()
158 	msm_uart_param(bas, baudrate, databits, stopbits, parity);  in msm_init()
164 	uart_setreg(bas, UART_DM_MR1, 0x0);  in msm_init()
167 	uart_setreg(bas, UART_DM_IMR, 0);  in msm_init()
174 	uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);  in msm_init()
177 	uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);  in msm_init()
183 	uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);  in msm_init()
186 	uart_setreg(bas, UART_DM_IRDA, 0x0);  in msm_init()
193 	uart_setreg(bas, UART_DM_HCR, 0x0);  in msm_init()
196 	SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);  in msm_init()
197 	SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);  in msm_init()
198 	SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);  in msm_init()
199 	SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);  in msm_init()
200 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_init()
203 	uart_setreg(bas, UART_DM_DMEN, UART_DM_DMEN_RX_SC_ENABLE);  in msm_init()
206 	uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);  in msm_init()
207 	uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);  in msm_init()
209 	uart_barrier(bas);  in msm_init()
213 msm_term(struct uart_bas *bas)  in msm_term()  argument
220 msm_putc(struct uart_bas *bas, int c)  in msm_putc()  argument
235 	if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {  in msm_putc()
236 		while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0  in msm_putc()
239 		SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);  in msm_putc()
242 	uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);  in msm_putc()
245 	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)  in msm_putc()
249 	SETREG(bas, UART_DM_TF(0), (c & 0xff));  in msm_putc()
253 msm_rxready(struct uart_bas *bas)  in msm_rxready()  argument
257 	return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==  in msm_rxready()
262 msm_getc(struct uart_bas *bas, struct mtx *mtx)  in msm_getc()  argument
269 	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=  in msm_getc()
274 	if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)  in msm_getc()
275 		uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);  in msm_getc()
278 	c = uart_getreg(bas, UART_DM_RF(0));  in msm_getc()
325 	struct uart_bas *bas;  in msm_bus_probe()  local
327 	bas = &sc->sc_bas;  in msm_bus_probe()
328 	bas->regiowidth = 4;  in msm_bus_probe()
342 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_attach()  local
351 	uart_setreg(bas, UART_DM_IMR, u->ier);  in msm_bus_attach()
363 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_transmit()  local
371 		msm_putc(bas, sc->sc_txbuf[i]);  in msm_bus_transmit()
372 		uart_barrier(bas);  in msm_bus_transmit()
377 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_transmit()
378 	uart_barrier(bas);  in msm_bus_transmit()
401 	struct uart_bas *bas;  in msm_bus_receive()  local
404 	bas = &sc->sc_bas;  in msm_bus_receive()
408 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_receive()
409 	SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);  in msm_bus_receive()
411 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_receive()
414 	while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {  in msm_bus_receive()
422 		c = uart_getreg(bas, UART_DM_RF(0));  in msm_bus_receive()
423 		uart_barrier(bas);  in msm_bus_receive()
456 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ipend()  local
463 	isr = GETREG(bas, UART_DM_MISR);  in msm_bus_ipend()
470 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
471 		uart_barrier(bas);  in msm_bus_ipend()
478 		SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);  in msm_bus_ipend()
479 		SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_ipend()
480 		uart_barrier(bas);  in msm_bus_ipend()
487 		SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);  in msm_bus_ipend()
491 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
492 		uart_barrier(bas);  in msm_bus_ipend()
501 		SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ipend()
502 		uart_barrier(bas);  in msm_bus_ipend()
536 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_grab()  local
543 	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);  in msm_bus_grab()
544 	SETREG(bas, UART_DM_IMR, 0);  in msm_bus_grab()
545 	uart_barrier(bas);  in msm_bus_grab()
553 	struct uart_bas *bas = &sc->sc_bas;  in msm_bus_ungrab()  local
559 	SETREG(bas, UART_DM_IMR, u->ier);  in msm_bus_ungrab()
560 	uart_barrier(bas);  in msm_bus_ungrab()