112 static void 		ad_write(struct mss_info *mss, int reg, u_char data);
418     	ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);  in mss_set_recsrc()
419     	ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);  in mss_set_recsrc()
456     	ad_write(mss, regoffs, val);  in mss_mixer_set()
467 		ad_write(mss, regoffs, val);  in mss_mixer_set()
492 		ad_write(mss, 20, 0x88);  in mssmix_init()
493 		ad_write(mss, 21, 0x88);  in mssmix_init()
505 		ad_write(mss, 22, 0x88);  in mssmix_init()
506 		ad_write(mss, 23, 0x88);  in mssmix_init()
702     		ad_write(mss, 10, 2); /* enable interrupts */  in mss_init()
733     		ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */  in mss_init()
734     		ad_write(mss, 0x19, 0); /* unmute left */  in mss_init()
735     		ad_write(mss, 0x1b, 0); /* unmute right */  in mss_init()
736     		ad_write(mss, 0x0c, tmp); /* restore old mode */  in mss_init()
759     		ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */  in mss_init()
761     	ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);  in mss_init()
763 	ad_write(mss, 10, 2); /* int enable */  in mss_init()
814 		if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */  in mss_intr()
859 ad_write(struct mss_info *mss, int reg, u_char data)  in ad_write()  function
873     	ad_write(mss, reg+1, cnt & 0xff);  in ad_write_cnt()
874     	ad_write(mss, reg, cnt >> 8); /* upper base must be last */  in ad_write_cnt()
912     	ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);  in ad_unmute()
913     	ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);  in ad_unmute()
968 		ad_write(mss, 22, (speed >> 8) & 0xff);	/* Speed MSB */  in mss_speed()
969 		ad_write(mss, 23, speed & 0xff);	/* Speed LSB */  in mss_speed()
981         	ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);  in mss_speed()
1021     	ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);  in mss_format()
1024 		ad_write(mss, 28, arg); /* capture mode */  in mss_format()
1067         	ad_write(mss, 9, m);  in mss_trigger()
1413     	ad_write(mss, 0, 0xaa);  in mss_detect()
1414     	ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */  in mss_detect()
1422     	ad_write(mss, 0, 0x45);  in mss_detect()
1423     	ad_write(mss, 1, 0xaa);  in mss_detect()
1437     	ad_write(mss, 12, (~tmp) & 0x0f);  in mss_detect()
1460     	ad_write(mss, 12, 0);	/* Mode2=disabled */  in mss_detect()
1482     	ad_write(mss, 12, 0x40);	/* Set mode2, clear 0x80 */  in mss_detect()
1494 	ad_write(mss, 16, 0);	/* Set I16 to known value */  in mss_detect()
1495 	ad_write(mss, 0, 0x45);  in mss_detect()
1498 	ad_write(mss, 0, 0xaa);  in mss_detect()
1505 	ad_write(mss, 25, ~tmp1);	/* Invert all bits */  in mss_detect()
1556 			ad_write(mss, 23, ~tmp);  in mss_detect()
1561 			ad_write(mss, 23, tmp);	/* Restore */  in mss_detect()
1581 	ad_write(mss, 25, tmp1);	/* Restore bits */  in mss_detect()
1827     			ad_write(mss, i, mss->mss_indexed_regs[i]);  in mss_resume()