168 #define	READ_REG(sc,r) \  macro
276 	sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &  in safe_attach()
379 	sc->sc_devinfo = READ_REG(sc, SAFE_DEVINFO);  in safe_attach()
532 	stat = READ_REG(sc, SAFE_HM_STAT);  in safe_intr()
578 			READ_REG(sc, SAFE_PE_DMASTAT)));  in safe_intr()
1420 	w = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1422 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1433 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1444 		READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN);  in safe_rng_disable_short_cycle()
1451 		READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);  in safe_rng_enable_short_cycle()
1460 	while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)  in safe_rng_read()
1462 	return READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_read()
1488 	if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {  in safe_rng()
1492 			READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));  in safe_rng()
1497 			w = READ_REG(sc, SAFE_RNG_CNFG);  in safe_rng()
1507 			if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {  in safe_rng()
1610 	v = READ_REG(sc, SAFE_PE_DMACFG) &~  in safe_reset_board()
1628 	v = READ_REG(sc, SAFE_PE_DMACFG);  in safe_init_board()
1653 			(READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,  in safe_init_board()
1812 		, READ_REG(sc, SAFE_DMA_ENDIAN)  in safe_dump_dmastatus()
1813 		, READ_REG(sc, SAFE_DMA_SRCADDR)  in safe_dump_dmastatus()
1814 		, READ_REG(sc, SAFE_DMA_DSTADDR)  in safe_dump_dmastatus()
1815 		, READ_REG(sc, SAFE_DMA_STAT)  in safe_dump_dmastatus()
1824 		, READ_REG(sc, SAFE_HI_CFG)  in safe_dump_intrstate()
1825 		, READ_REG(sc, SAFE_HI_MASK)  in safe_dump_intrstate()
1826 		, READ_REG(sc, SAFE_HI_DESC_CNT)  in safe_dump_intrstate()
1827 		, READ_REG(sc, SAFE_HU_STAT)  in safe_dump_intrstate()
1828 		, READ_REG(sc, SAFE_HM_STAT)  in safe_dump_intrstate()
1835 	u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);  in safe_dump_ringstate()