1362 		bus_write_1(bar->b_res, REG_SPR, REG_ACR);  in puc_config_advantech()
1363 		bus_write_1(bar->b_res, REG_ICR, acr);  in puc_config_advantech()
1475 		bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);  in puc_config_quatech()
1476 		bus_write_1(bar->b_res, REG_SPR, 0);  in puc_config_quatech()
1478 		bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);  in puc_config_quatech()
1480 		bus_write_1(bar->b_res, REG_LCR, 0);  in puc_config_quatech()
1567 		bus_write_1(bar->b_res, 0x250, 0x89);  in puc_config_syba()
1568 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
1569 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
1573 			bus_write_1(bar->b_res, efir, 0x09);  in puc_config_syba()
1577 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1579 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1580 			bus_write_1(bar->b_res, efir + 1, v | 0x04);  in puc_config_syba()
1581 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1582 			bus_write_1(bar->b_res, efir + 1, v & ~0x04);  in puc_config_syba()
1584 			bus_write_1(bar->b_res, efir, 0x23);  in puc_config_syba()
1585 			bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);  in puc_config_syba()
1586 			bus_write_1(bar->b_res, efir, 0x24);  in puc_config_syba()
1587 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);  in puc_config_syba()
1588 			bus_write_1(bar->b_res, efir, 0x25);  in puc_config_syba()
1589 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);  in puc_config_syba()
1590 			bus_write_1(bar->b_res, efir, 0x17);  in puc_config_syba()
1591 			bus_write_1(bar->b_res, efir + 1, 0x03);  in puc_config_syba()
1592 			bus_write_1(bar->b_res, efir, 0x28);  in puc_config_syba()
1593 			bus_write_1(bar->b_res, efir + 1, 0x43);  in puc_config_syba()
1596 		bus_write_1(bar->b_res, 0x250, 0xaa);  in puc_config_syba()
1597 		bus_write_1(bar->b_res, 0x3f0, 0xaa);  in puc_config_syba()
1776 			bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,  in puc_config_oxford_pcie()