Lines Matching defs:mly_param_controller

156 struct mly_param_controller {  struct
157     u_int8_t	rdahen:1;					/* N/A */
158     u_int8_t	bilodly:1;					/* N/A */
159     u_int8_t   	fua_disable:1;
160     u_int8_t	reass1s:1;					/* N/A */
161     u_int8_t	truvrfy:1;					/* N/A */
162     u_int8_t	dwtvrfy:1;					/* N/A */
163     u_int8_t	background_initialisation:1;
164     u_int8_t	clustering:1;					/* N/A */
166     u_int8_t	bios_disable:1;
167     u_int8_t   	boot_from_cdrom:1;
168     u_int8_t	drive_coercion:1;
169     u_int8_t	write_same_disable:1;
170     u_int8_t	hba_mode:1;					/* N/A */
171     u_int8_t	bios_geometry:2;
174     u_int8_t	res1:1;						/* N/A */
176     u_int8_t	res2[2];					/* N/A */
178     u_int8_t	v_dec:1;
179     u_int8_t	safte:1;					/* N/A */
180     u_int8_t	ses:1;						/* N/A */
181     u_int8_t	res3:2;						/* N/A */
182     u_int8_t	v_arm:1;
183     u_int8_t	v_ofm:1;
184     u_int8_t	res4:1;						/* N/A */
186     u_int8_t	rebuild_check_rate;
187     u_int8_t	cache_line_size;	/* see 8.4 */
188     u_int8_t	oem_code;
195     u_int8_t	spinup_mode;
199     u_int8_t	spinup_devices;
200     u_int8_t	spinup_interval;
201     u_int8_t	spinup_wait_time;
203     u_int8_t	res5:3;						/* N/A */
204     u_int8_t	vutursns:1;					/* N/A */
205     u_int8_t	dccfil:1;					/* N/A */
206     u_int8_t	nopause:1;					/* N/A */
207     u_int8_t	disqfull:1;					/* N/A */
208     u_int8_t	disbusy:1;					/* N/A */
210     u_int8_t	res6:2;						/* N/A */
211     u_int8_t	failover_node_name;				/* N/A */
212     u_int8_t	res7:1;						/* N/A */
213     u_int8_t	ftopo:3;					/* N/A */
214     u_int8_t	disable_ups:1;					/* N/A */
216     u_int8_t	res8:1;						/* N/A */
217     u_int8_t	propagate_reset:1;				/* N/A */
218     u_int8_t	nonstd_mp_reset:1;				/* N/A */
219     u_int8_t	res9:5;						/* N/A */
221     u_int8_t	res10;						/* N/A */
222     u_int8_t	serial_port_baud_rate;				/* N/A */
223     u_int8_t	serial_port_control;				/* N/A */
224     u_int8_t	change_stripe_ok_developer_flag_only;		/* N/A */
226     u_int8_t	small_large_host_transfers:2;			/* N/A */
227     u_int8_t	frame_control:2;				/* N/A */
228     u_int8_t	pci_latency_control:2;				/* N/A */
229     u_int8_t	treat_lip_as_reset:1;				/* N/A */
230     u_int8_t	res11:1;					/* N/A */
232     u_int8_t	ms_autorest:1;					/* N/A */
233     u_int8_t	res12:7;					/* N/A */
235     u_int8_t	ms_aa_fsim:1;					/* N/A */
236     u_int8_t	ms_aa_ccach:1;					/* N/A */
237     u_int8_t	ms_aa_fault_signals:1;				/* N/A */
238     u_int8_t	ms_aa_c4_faults:1;				/* N/A */
239     u_int8_t	ms_aa_host_reset_delay_mask:4;			/* N/A */
241     u_int8_t	ms_flg_simplex_no_rstcom:1;			/* N/A */
242     u_int8_t	res13:7;					/* N/A */
244     u_int8_t	res14;						/* N/A */
245     u_int8_t	hardloopid[2][2];				/* N/A */
246     u_int8_t	ctrlname[2][16+1];				/* N/A */
247     u_int8_t	initiator_id;
248     u_int8_t	startup_option;
256     u_int8_t	res15[62];