759 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
950 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
2252 				   params->phy[phy_index].mdio_ctrl);  in elink_set_mdio_emac_per_phy()
2545 	if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {  in elink_xmac_enable()
2576 	    (params->phy[ELINK_INT_PHY].supported &  in elink_xmac_enable()
3415 				       struct elink_phy *phy,  in elink_cl22_write()  argument
3422 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_write()
3423 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_write()
3427 	tmp = ((phy->addr << 21) | (reg << 16) | val |  in elink_cl22_write()
3430 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl22_write()
3435 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_write()
3445 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_write()
3450 				      struct elink_phy *phy,  in elink_cl22_read()  argument
3458 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_read()
3459 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_read()
3463 	val = ((phy->addr << 21) | (reg << 16) |  in elink_cl22_read()
3466 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl22_read()
3471 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_read()
3484 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_read()
3491 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_read()  argument
3498 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {  in elink_cl45_read()
3501 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_read()
3504 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_read()
3505 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3508 	val = ((phy->addr << 21) | (devad << 16) | reg |  in elink_cl45_read()
3511 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3516 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_read()
3530 		val = ((phy->addr << 21) | (devad << 16) |  in elink_cl45_read()
3533 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3538 			val = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_read()
3554 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {  in elink_cl45_read()
3555 		phy->flags ^= ELINK_FLAGS_DUMMY_READ;  in elink_cl45_read()
3556 		if (phy->flags & ELINK_FLAGS_DUMMY_READ) {  in elink_cl45_read()
3558 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_read()
3562 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_read()
3563 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3568 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_write()  argument
3575 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {  in elink_cl45_write()
3578 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_write()
3581 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_write()
3582 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3586 	tmp = ((phy->addr << 21) | (devad << 16) | reg |  in elink_cl45_write()
3589 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3594 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_write()
3607 		tmp = ((phy->addr << 21) | (devad << 16) | val |  in elink_cl45_write()
3610 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3615 			tmp = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_write()
3630 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {  in elink_cl45_write()
3631 		phy->flags ^= ELINK_FLAGS_DUMMY_READ;  in elink_cl45_write()
3632 		if (phy->flags & ELINK_FLAGS_DUMMY_READ) {  in elink_cl45_write()
3634 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_write()
3637 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_write()
3638 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3781 static elink_status_t elink_eee_disable(struct elink_phy *phy,  in elink_eee_disable()  argument
3790 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);  in elink_eee_disable()
3797 static elink_status_t elink_eee_advertise(struct elink_phy *phy,  in elink_eee_advertise()  argument
3816 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);  in elink_eee_advertise()
3834 static void elink_eee_an_resolve(struct elink_phy *phy,  in elink_eee_an_resolve()  argument
3843 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);  in elink_eee_an_resolve()
3844 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);  in elink_eee_an_resolve()
3994 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_read_or_write()  argument
3998 	elink_cl45_read(sc, phy, devad, reg, &val);  in elink_cl45_read_or_write()
3999 	elink_cl45_write(sc, phy, devad, reg, val | or_val);  in elink_cl45_read_or_write()
4003 				      struct elink_phy *phy,  in elink_cl45_read_and_write()  argument
4007 	elink_cl45_read(sc, phy, devad, reg, &val);  in elink_cl45_read_and_write()
4008 	elink_cl45_write(sc, phy, devad, reg, val & and_val);  in elink_cl45_read_and_write()
4019 		if (params->phy[phy_index].addr == phy_addr) {  in elink_phy_read()
4021 					       &params->phy[phy_index], devad,  in elink_phy_read()
4036 		if (params->phy[phy_index].addr == phy_addr) {  in elink_phy_write()
4038 						&params->phy[phy_index], devad,  in elink_phy_write()
4045 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,  in elink_get_warpcore_lane()  argument
4101 			      struct elink_phy *phy)  in elink_set_aer_mmd()  argument
4110 	offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?  in elink_set_aer_mmd()
4111 		(phy->addr + ser_lane) : 0;  in elink_set_aer_mmd()
4114 		aer_val = elink_get_warpcore_lane(phy, params);  in elink_set_aer_mmd()
4121 		if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_set_aer_mmd()
4128 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_set_aer_mmd()
4170 static void elink_xgxs_specific_func(struct elink_phy *phy,  in elink_xgxs_specific_func()  argument
4180 		       phy->def_md_devad);  in elink_xgxs_specific_func()
4199 	elink_xgxs_specific_func(&params->phy[ELINK_INT_PHY], params,  in elink_xgxs_deassert()
4203 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,  in elink_calc_ieee_aneg_adv()  argument
4212 	switch (phy->req_flow_ctrl) {  in elink_calc_ieee_aneg_adv()
4261 		params->phy[actual_phy_idx].req_flow_ctrl =  in set_phy_vars()
4264 		params->phy[actual_phy_idx].req_line_speed =  in set_phy_vars()
4267 		params->phy[actual_phy_idx].speed_cap_mask =  in set_phy_vars()
4270 		params->phy[actual_phy_idx].req_duplex =  in set_phy_vars()
4279 			   params->phy[actual_phy_idx].req_flow_ctrl,  in set_phy_vars()
4280 			   params->phy[actual_phy_idx].req_line_speed,  in set_phy_vars()
4281 			   params->phy[actual_phy_idx].speed_cap_mask);  in set_phy_vars()
4286 				    struct elink_phy *phy,  in elink_ext_phy_set_pause()  argument
4292 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);  in elink_ext_phy_set_pause()
4297 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_ext_phy_set_pause()
4309 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);  in elink_ext_phy_set_pause()
4312 static void elink_pause_resolve(struct elink_phy *phy,  in elink_pause_resolve()  argument
4359 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,  in elink_ext_phy_update_adv_fc()  argument
4367 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {  in elink_ext_phy_update_adv_fc()
4368 		elink_cl22_read(sc, phy, 0x4, &ld_pause);  in elink_ext_phy_update_adv_fc()
4369 		elink_cl22_read(sc, phy, 0x5, &lp_pause);  in elink_ext_phy_update_adv_fc()
4372 		uint8_t lane = elink_get_warpcore_lane(phy, params);  in elink_ext_phy_update_adv_fc()
4374 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4381 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4383 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4386 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4388 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4398 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4401 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4410 	elink_pause_resolve(phy, params, vars, pause_result);  in elink_ext_phy_update_adv_fc()
4414 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,  in elink_ext_phy_resolve_fc()  argument
4420 	if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {  in elink_ext_phy_resolve_fc()
4422 		if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_ext_phy_resolve_fc()
4423 			elink_ext_phy_update_adv_fc(phy, params, vars);  in elink_ext_phy_resolve_fc()
4425 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_ext_phy_resolve_fc()
4426 	} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_ext_phy_resolve_fc()
4430 		elink_ext_phy_update_adv_fc(phy, params, vars);  in elink_ext_phy_resolve_fc()
4463 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,  in elink_warpcore_enable_AN_KR2()  argument
4490 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR2()
4494 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_enable_AN_KR2()
4504 			      struct elink_phy *phy)  in elink_disable_kr2()  argument
4529 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_disable_kr2()
4537 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,  in elink_warpcore_set_lpi_passthrough()  argument
4543 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_lpi_passthrough()
4545 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_lpi_passthrough()
4549 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,  in elink_warpcore_restart_AN_KR()  argument
4554 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_restart_AN_KR()
4555 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_restart_AN_KR()
4557 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_restart_AN_KR()
4561 	elink_set_aer_mmd(params, phy);  in elink_warpcore_restart_AN_KR()
4564 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,  in elink_warpcore_enable_AN_KR()  argument
4583 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_enable_AN_KR()
4586 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4590 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4595 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||  in elink_warpcore_enable_AN_KR()
4601 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);  in elink_warpcore_enable_AN_KR()
4605 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||  in elink_warpcore_enable_AN_KR()
4610 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_enable_AN_KR()
4613 		elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4615 		elink_set_aer_mmd(params, phy);  in elink_warpcore_enable_AN_KR()
4620 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_enable_AN_KR()
4621 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4625 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_warpcore_enable_AN_KR()
4626 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4629 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4632 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4637 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4641 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4651 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4658 	elink_ext_phy_set_pause(params, phy, vars);  in elink_warpcore_enable_AN_KR()
4660 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4664 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4667 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_warpcore_enable_AN_KR()
4668 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||  in elink_warpcore_enable_AN_KR()
4669 	    (phy->req_line_speed == ELINK_SPEED_20000)) {  in elink_warpcore_enable_AN_KR()
4671 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_enable_AN_KR()
4674 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4678 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4680 		elink_set_aer_mmd(params, phy);  in elink_warpcore_enable_AN_KR()
4682 		elink_warpcore_enable_AN_KR2(phy, params, vars);  in elink_warpcore_enable_AN_KR()
4685 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4690 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4705 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4709 		elink_disable_kr2(params, vars, phy);  in elink_warpcore_enable_AN_KR()
4713 	elink_warpcore_restart_AN_KR(phy, params);  in elink_warpcore_enable_AN_KR()
4716 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,  in elink_warpcore_set_10G_KR()  argument
4736 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_set_10G_KR()
4739 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_10G_KR()
4741 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_10G_KR()
4744 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4747 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4750 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4753 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4756 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_10G_KR()
4758 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_10G_KR()
4761 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_10G_KR()
4765 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4769 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4773 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4777 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4779 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4784 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,  in elink_warpcore_set_10G_XFI()  argument
4793 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4797 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4801 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);  in elink_warpcore_set_10G_XFI()
4804 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4808 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4812 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4816 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4821 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4823 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4828 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4884 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4888 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_10G_XFI()
4889 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4892 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4897 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4901 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4904 	elink_warpcore_set_lpi_passthrough(phy, params);  in elink_warpcore_set_10G_XFI()
4907 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4911 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4915 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4919 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,  in elink_warpcore_set_20G_force_KR2()  argument
4925 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_20G_force_KR2()
4929 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4932 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_20G_force_KR2()
4934 	elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4936 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4939 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4943 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4947 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4950 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4953 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4957 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4959 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4963 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_20G_force_KR2()
4966 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4969 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_20G_force_KR2()
4973 					 struct elink_phy *phy,  in elink_warpcore_set_20G_DXGXS()  argument
4977 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4981 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4984 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4987 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4990 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4993 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4996 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4999 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5002 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5005 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5009 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5013 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5017 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5021 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5026 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,  in elink_warpcore_set_sgmii_speed()  argument
5035 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5038 	elink_warpcore_set_lpi_passthrough(phy, params);  in elink_warpcore_set_sgmii_speed()
5040 	if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_warpcore_set_sgmii_speed()
5042 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5047 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5050 		switch (phy->req_line_speed) {  in elink_warpcore_set_sgmii_speed()
5061 			   "Speed not supported: 0x%x\n", phy->req_line_speed);  in elink_warpcore_set_sgmii_speed()
5065 		if (phy->req_duplex == DUPLEX_FULL)  in elink_warpcore_set_sgmii_speed()
5068 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5072 			       phy->req_line_speed);  in elink_warpcore_set_sgmii_speed()
5073 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5079 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5086 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5091 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5093 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5098 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5103 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5110 				      struct elink_phy *phy,  in elink_warpcore_reset_lane()  argument
5115 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5121 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5123 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5128 static void elink_warpcore_clear_regs(struct elink_phy *phy,  in elink_warpcore_clear_regs()  argument
5151 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_clear_regs()
5155 		elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,  in elink_warpcore_clear_regs()
5158 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_clear_regs()
5159 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_clear_regs()
5203 static int elink_is_sfp_module_plugged(struct elink_phy *phy,  in elink_is_sfp_module_plugged()  argument
5221 static int elink_warpcore_get_sigdet(struct elink_phy *phy,  in elink_warpcore_get_sigdet()  argument
5227 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_get_sigdet()
5229 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,  in elink_warpcore_get_sigdet()
5235 static void elink_warpcore_config_runtime(struct elink_phy *phy,  in elink_warpcore_config_runtime()  argument
5249 		uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_runtime()
5258 			elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,  in elink_warpcore_config_runtime()
5268 				elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_config_runtime()
5269 				elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_runtime()
5272 				elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_config_runtime()
5288 static void elink_warpcore_config_sfi(struct elink_phy *phy,  in elink_warpcore_config_sfi()  argument
5291 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_sfi()
5293 	elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_sfi()
5296 	    (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {  in elink_warpcore_config_sfi()
5298 		elink_warpcore_set_10G_XFI(phy, params, 0);  in elink_warpcore_config_sfi()
5301 		elink_warpcore_set_sgmii_speed(phy, params, 1, 0);  in elink_warpcore_config_sfi()
5306 					 struct elink_phy *phy,  in elink_sfp_e3_set_transmitter()  argument
5322 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)  in elink_sfp_e3_set_transmitter()
5326 static void elink_warpcore_config_init(struct elink_phy *phy,  in elink_warpcore_config_init()  argument
5333 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_init()
5341 	elink_set_aer_mmd(params, phy);  in elink_warpcore_config_init()
5342 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_config_init()
5345 	    (phy->req_line_speed &&  in elink_warpcore_config_init()
5346 	     ((phy->req_line_speed == ELINK_SPEED_100) ||  in elink_warpcore_config_init()
5347 	      (phy->req_line_speed == ELINK_SPEED_10)))) {  in elink_warpcore_config_init()
5350 		elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_init()
5351 		elink_warpcore_set_sgmii_speed(phy, params, 0, 1);  in elink_warpcore_config_init()
5357 				elink_warpcore_enable_AN_KR(phy, params, vars);  in elink_warpcore_config_init()
5360 				elink_warpcore_set_10G_KR(phy, params, vars);  in elink_warpcore_config_init()
5365 			elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_init()
5368 				elink_warpcore_set_10G_XFI(phy, params, 1);  in elink_warpcore_config_init()
5377 				elink_warpcore_set_sgmii_speed(phy,  in elink_warpcore_config_init()
5392 				if (elink_is_sfp_module_plugged(phy, params))  in elink_warpcore_config_init()
5393 					elink_sfp_module_detection(phy, params);  in elink_warpcore_config_init()
5396 								     phy, 1);  in elink_warpcore_config_init()
5399 			elink_warpcore_config_sfi(phy, params);  in elink_warpcore_config_init()
5408 			elink_warpcore_set_20G_DXGXS(sc, phy, lane);  in elink_warpcore_config_init()
5411 			elink_sfp_module_detection(phy, params);  in elink_warpcore_config_init()
5415 				elink_warpcore_enable_AN_KR(phy, params, vars);  in elink_warpcore_config_init()
5418 				elink_warpcore_set_20G_force_KR2(phy, params);  in elink_warpcore_config_init()
5430 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_init()
5434 static void elink_warpcore_link_reset(struct elink_phy *phy,  in elink_warpcore_link_reset()  argument
5439 	elink_sfp_e3_set_transmitter(params, phy, 0);  in elink_warpcore_link_reset()
5441 	elink_set_aer_mmd(params, phy);  in elink_warpcore_link_reset()
5443 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_link_reset()
5447 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5450 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5454 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_link_reset()
5457 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5461 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5463 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_link_reset()
5465 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5468 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_warpcore_link_reset()
5470 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5473 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5477 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {  in elink_warpcore_link_reset()
5482 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5485 	elink_set_aer_mmd(params, phy);  in elink_warpcore_link_reset()
5489 static void elink_set_warpcore_loopback(struct elink_phy *phy,  in elink_set_warpcore_loopback()  argument
5496 		       params->loopback_mode, phy->req_line_speed);  in elink_set_warpcore_loopback()
5498 	if (phy->req_line_speed < ELINK_SPEED_10000 ||  in elink_set_warpcore_loopback()
5499 	    phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {  in elink_set_warpcore_loopback()
5503 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_set_warpcore_loopback()
5506 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5510 		lane = elink_get_warpcore_lane(phy, params);  in elink_set_warpcore_loopback()
5511 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5514 		if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_set_warpcore_loopback()
5516 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5521 		elink_set_aer_mmd(params, phy);  in elink_set_warpcore_loopback()
5524 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5527 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5672 	params->phy[ELINK_INT_PHY].media_type =  in elink_link_status_update()
5675 	params->phy[ELINK_EXT_PHY1].media_type =  in elink_link_status_update()
5678 	params->phy[ELINK_EXT_PHY2].media_type =  in elink_link_status_update()
5709 				struct elink_phy *phy)  in elink_set_master_ln()  argument
5718 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_master_ln()
5723 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_master_ln()
5730 			       struct elink_phy *phy,  in elink_reset_unicore()  argument
5736 	CL22_RD_OVER_CL45(sc, phy,  in elink_reset_unicore()
5741 	CL22_WR_OVER_CL45(sc, phy,  in elink_reset_unicore()
5754 		CL22_RD_OVER_CL45(sc, phy,  in elink_reset_unicore()
5774 				 struct elink_phy *phy)  in elink_set_swap_lanes()  argument
5790 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5797 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5803 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5809 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5815 static void elink_set_parallel_detection(struct elink_phy *phy,  in elink_set_parallel_detection()  argument
5820 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5824 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)  in elink_set_parallel_detection()
5829 		phy->speed_cap_mask, control2);  in elink_set_parallel_detection()
5830 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5835 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&  in elink_set_parallel_detection()
5836 	     (phy->speed_cap_mask &  in elink_set_parallel_detection()
5840 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5845 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5854 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5860 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5868 static void elink_set_autoneg(struct elink_phy *phy,  in elink_set_autoneg()  argument
5877 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5888 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5894 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5905 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5910 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5923 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5930 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5936 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5944 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5948 		if (phy->speed_cap_mask &  in elink_set_autoneg()
5951 		if (phy->speed_cap_mask &  in elink_set_autoneg()
5955 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5966 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5972 static void elink_program_serdes(struct elink_phy *phy,  in elink_program_serdes()  argument
5980 	CL22_RD_OVER_CL45(sc, phy,  in elink_program_serdes()
5986 	if (phy->req_duplex == DUPLEX_FULL)  in elink_program_serdes()
5988 	CL22_WR_OVER_CL45(sc, phy,  in elink_program_serdes()
5995 	CL22_RD_OVER_CL45(sc, phy,  in elink_program_serdes()
6015 	CL22_WR_OVER_CL45(sc, phy,  in elink_program_serdes()
6021 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,  in elink_set_brcm_cl37_advertisement()  argument
6028 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)  in elink_set_brcm_cl37_advertisement()
6030 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)  in elink_set_brcm_cl37_advertisement()
6032 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_brcm_cl37_advertisement()
6036 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_brcm_cl37_advertisement()
6041 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,  in elink_set_ieee_aneg_advertisement()  argument
6049 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6052 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6057 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6062 static void elink_restart_autoneg(struct elink_phy *phy,  in elink_restart_autoneg()  argument
6073 		CL22_RD_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6078 		CL22_WR_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6086 		CL22_RD_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6093 		CL22_WR_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6102 static void elink_initialize_sgmii_process(struct elink_phy *phy,  in elink_initialize_sgmii_process()  argument
6111 	CL22_RD_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6120 	CL22_WR_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6130 		CL22_RD_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6158 		if (phy->req_duplex == DUPLEX_FULL)  in elink_initialize_sgmii_process()
6161 		CL22_WR_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6168 		elink_restart_autoneg(phy, params, 0);  in elink_initialize_sgmii_process()
6174 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,  in elink_direct_parallel_detect_used()  argument
6179 	if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_direct_parallel_detect_used()
6181 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6185 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6195 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6208 static void elink_update_adv_fc(struct elink_phy *phy,  in elink_update_adv_fc()  argument
6223 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6227 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6237 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6241 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6251 	elink_pause_resolve(phy, params, vars, pause_result);  in elink_update_adv_fc()
6255 static void elink_flow_ctrl_resolve(struct elink_phy *phy,  in elink_flow_ctrl_resolve()  argument
6264 	if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {  in elink_flow_ctrl_resolve()
6266 		if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_flow_ctrl_resolve()
6267 			elink_update_adv_fc(phy, params, vars, gp_status);  in elink_flow_ctrl_resolve()
6269 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_flow_ctrl_resolve()
6270 	} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_flow_ctrl_resolve()
6274 		if (elink_direct_parallel_detect_used(phy, params)) {  in elink_flow_ctrl_resolve()
6278 		elink_update_adv_fc(phy, params, vars, gp_status);  in elink_flow_ctrl_resolve()
6283 static void elink_check_fallback_to_cl37(struct elink_phy *phy,  in elink_check_fallback_to_cl37()  argument
6290 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6298 		CL22_WR_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6305 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6321 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6342 	CL22_WR_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6347 	elink_restart_autoneg(phy, params, 0);  in elink_check_fallback_to_cl37()
6351 static void elink_xgxs_an_resolve(struct elink_phy *phy,  in elink_xgxs_an_resolve()  argument
6360 	if (elink_direct_parallel_detect_used(phy, params))  in elink_xgxs_an_resolve()
6364 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,  in elink_get_link_speed_duplex()  argument
6372 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_get_link_speed_duplex()
6457 static elink_status_t elink_link_settings_status(struct elink_phy *phy,  in elink_link_settings_status()  argument
6467 	CL22_RD_OVER_CL45(sc, phy,  in elink_link_settings_status()
6486 	rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,  in elink_link_settings_status()
6494 			elink_flow_ctrl_resolve(phy, params, vars, gp_status);  in elink_link_settings_status()
6495 			if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_link_settings_status()
6496 				elink_xgxs_an_resolve(phy, params, vars,  in elink_link_settings_status()
6500 		if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_link_settings_status()
6503 			elink_check_fallback_to_cl37(phy, params);  in elink_link_settings_status()
6512 		CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,  in elink_link_settings_status()
6523 		CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,  in elink_link_settings_status()
6539 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,  in elink_warpcore_read_status()  argument
6547 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_read_status()
6550 	    (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {  in elink_warpcore_read_status()
6551 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6553 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6558 	} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&  in elink_warpcore_read_status()
6559 		(phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {  in elink_warpcore_read_status()
6561 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6563 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6569 			elink_ext_phy_resolve_fc(phy, params, vars);  in elink_warpcore_read_status()
6571 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6580 		if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {  in elink_warpcore_read_status()
6582 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6584 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6592 			if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_warpcore_read_status()
6594 				elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6602 				elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6611 			elink_ext_phy_resolve_fc(phy, params, vars);  in elink_warpcore_read_status()
6623 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6635 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6651 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6654 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6665 	rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,  in elink_warpcore_read_status()
6669 	if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&  in elink_warpcore_read_status()
6670 	    (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))  in elink_warpcore_read_status()
6680 	struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_set_gmii_tx_driver()  local
6686 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6700 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6709 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6763 static void elink_set_preemphasis(struct elink_phy *phy,  in elink_set_preemphasis()  argument
6772 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_preemphasis()
6775 					  phy->rx_preemphasis[i]);  in elink_set_preemphasis()
6780 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_preemphasis()
6783 					  phy->tx_preemphasis[i]);  in elink_set_preemphasis()
6787 static void elink_xgxs_config_init(struct elink_phy *phy,  in elink_xgxs_config_init()  argument
6798 			elink_set_preemphasis(phy, params);  in elink_xgxs_config_init()
6807 			elink_set_autoneg(phy, params, vars, 0);  in elink_xgxs_config_init()
6810 			elink_program_serdes(phy, params, vars);  in elink_xgxs_config_init()
6816 			elink_set_brcm_cl37_advertisement(phy, params);  in elink_xgxs_config_init()
6819 			elink_set_ieee_aneg_advertisement(phy, params,  in elink_xgxs_config_init()
6823 			elink_set_autoneg(phy, params, vars, enable_cl73);  in elink_xgxs_config_init()
6826 			elink_restart_autoneg(phy, params, enable_cl73);  in elink_xgxs_config_init()
6832 		elink_initialize_sgmii_process(phy, params, vars);  in elink_xgxs_config_init()
6836 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,  in elink_prepare_xgxs()  argument
6842 	if ((phy->req_line_speed &&  in elink_prepare_xgxs()
6843 	     ((phy->req_line_speed == ELINK_SPEED_100) ||  in elink_prepare_xgxs()
6844 	      (phy->req_line_speed == ELINK_SPEED_10))) ||  in elink_prepare_xgxs()
6845 	    (!phy->req_line_speed &&  in elink_prepare_xgxs()
6846 	     (phy->speed_cap_mask >=  in elink_prepare_xgxs()
6848 	     (phy->speed_cap_mask <  in elink_prepare_xgxs()
6850 	    (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))  in elink_prepare_xgxs()
6855 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_prepare_xgxs()
6856 	elink_set_aer_mmd(params, phy);  in elink_prepare_xgxs()
6857 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_prepare_xgxs()
6858 		elink_set_master_ln(params, phy);  in elink_prepare_xgxs()
6860 	rc = elink_reset_unicore(params, phy, 0);  in elink_prepare_xgxs()
6865 	elink_set_aer_mmd(params, phy);  in elink_prepare_xgxs()
6867 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {  in elink_prepare_xgxs()
6868 		elink_set_master_ln(params, phy);  in elink_prepare_xgxs()
6869 		elink_set_swap_lanes(params, phy);  in elink_prepare_xgxs()
6876 				     struct elink_phy *phy,  in elink_wait_reset_complete()  argument
6882 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)  in elink_wait_reset_complete()
6883 			elink_cl22_read(sc, phy,  in elink_wait_reset_complete()
6886 			elink_cl45_read(sc, phy,  in elink_wait_reset_complete()
6918 			params->phy[ELINK_INT_PHY].type !=  in elink_link_int_enable()
6928 			params->phy[ELINK_INT_PHY].type !=  in elink_link_int_enable()
7084 	spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);  in elink_get_ext_phy_fw_version()
7086 	if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {  in elink_get_ext_phy_fw_version()
7087 		status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,  in elink_get_ext_phy_fw_version()
7093 	    (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {  in elink_get_ext_phy_fw_version()
7094 		spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);  in elink_get_ext_phy_fw_version()
7095 		if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {  in elink_get_ext_phy_fw_version()
7099 			status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(  in elink_get_ext_phy_fw_version()
7110 static void elink_set_xgxs_loopback(struct elink_phy *phy,  in elink_set_xgxs_loopback()  argument
7116 	if (phy->req_line_speed != ELINK_SPEED_1000) {  in elink_set_xgxs_loopback()
7130 		elink_cl45_write(sc, phy,  in elink_set_xgxs_loopback()
7136 		elink_cl45_write(sc, phy,  in elink_set_xgxs_loopback()
7143 		elink_set_aer_mmd(params, phy);  in elink_set_xgxs_loopback()
7153 		elink_cl45_read(sc, phy, 5,  in elink_set_xgxs_loopback()
7157 		elink_cl45_write(sc, phy, 5,  in elink_set_xgxs_loopback()
7180 		if (params->phy[phy_idx].set_link_led) {  in elink_set_led()
7181 			params->phy[phy_idx].set_link_led(  in elink_set_led()
7182 				&params->phy[phy_idx], params, mode);  in elink_set_led()
7199 		if (params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7217 		if (((params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7219 			 (params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7255 		} else if ((params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7325 	struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];  in elink_test_link()
7375 		ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(  in elink_test_link()
7376 			&params->phy[ELINK_EXT_PHY1],  in elink_test_link()
7382 			serdes_phy_type = ((params->phy[phy_index].media_type ==  in elink_test_link()
7384 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7386 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7388 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7393 			if (params->phy[phy_index].read_status) {  in elink_test_link()
7395 					params->phy[phy_index].read_status(  in elink_test_link()
7396 						&params->phy[phy_index],  in elink_test_link()
7417 	vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;  in elink_link_initialize()
7424 		elink_prepare_xgxs(&params->phy[ELINK_INT_PHY], params, vars);  in elink_link_initialize()
7430 	    (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||  in elink_link_initialize()
7432 		struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_link_initialize()  local
7436 			elink_set_parallel_detection(phy, params);  in elink_link_initialize()
7437 		if (params->phy[ELINK_INT_PHY].config_init)  in elink_link_initialize()
7438 			params->phy[ELINK_INT_PHY].config_init(phy, params, vars);  in elink_link_initialize()
7444 	vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;  in elink_link_initialize()
7448 		if (params->phy[ELINK_INT_PHY].supported &  in elink_link_initialize()
7459 			if (params->phy[phy_index].supported &  in elink_link_initialize()
7470 			params->phy[phy_index].config_init(  in elink_link_initialize()
7471 				&params->phy[phy_index],  in elink_link_initialize()
7485 static void elink_int_link_reset(struct elink_phy *phy,  in elink_int_link_reset()  argument
7493 static void elink_common_ext_link_reset(struct elink_phy *phy,  in elink_common_ext_link_reset()  argument
7641 		if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {  in elink_update_link_up()
7707 		elink_set_aer_mmd(params, &params->phy[ELINK_INT_PHY]);  in elink_link_update()
7735 		struct elink_phy *phy = &params->phy[phy_index];  in elink_link_update()  local
7736 		if (!phy->read_status)  in elink_link_update()
7739 		cur_link_up = phy->read_status(phy, params,  in elink_link_update()
7793 	if (params->phy[ELINK_INT_PHY].read_status)  in elink_link_update()
7794 		params->phy[ELINK_INT_PHY].read_status(  in elink_link_update()
7795 			&params->phy[ELINK_INT_PHY],  in elink_link_update()
7815 			if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {  in elink_link_update()
7818 				params->phy[ELINK_EXT_PHY2].phy_specific_func(  in elink_link_update()
7819 					&params->phy[ELINK_EXT_PHY2],  in elink_link_update()
7826 		if (params->phy[active_external_phy].supported &  in elink_link_update()
7853 		if (params->phy[phy_index].flags &  in elink_link_update()
7901 			   params->phy[ELINK_EXT_PHY1].flags &  in elink_link_update()
7903 		if (!(params->phy[ELINK_EXT_PHY1].flags &  in elink_link_update()
7912 			if (params->phy[ELINK_INT_PHY].config_init)  in elink_link_update()
7913 				params->phy[ELINK_INT_PHY].config_init(  in elink_link_update()
7914 					&params->phy[ELINK_INT_PHY], params,  in elink_link_update()
7976 				      struct elink_phy *phy,  in elink_save_bcm_spirom_ver()  argument
7981 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_save_bcm_spirom_ver()
7983 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_save_bcm_spirom_ver()
7986 				  phy->ver_addr);  in elink_save_bcm_spirom_ver()
7990 				       struct elink_phy *phy,  in elink_ext_phy_10G_an_resolve()  argument
7994 	elink_cl45_read(sc, phy,  in elink_ext_phy_10G_an_resolve()
7997 	elink_cl45_read(sc, phy,  in elink_ext_phy_10G_an_resolve()
8009 static void elink_8073_resolve_fc(struct elink_phy *phy,  in elink_8073_resolve_fc()  argument
8014 	if (phy->req_line_speed == ELINK_SPEED_10 ||  in elink_8073_resolve_fc()
8015 	    phy->req_line_speed == ELINK_SPEED_100) {  in elink_8073_resolve_fc()
8016 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_8073_resolve_fc()
8020 	if (elink_ext_phy_resolve_fc(phy, params, vars) &&  in elink_8073_resolve_fc()
8025 		elink_cl45_read(sc, phy,  in elink_8073_resolve_fc()
8029 		elink_cl45_read(sc, phy,  in elink_8073_resolve_fc()
8037 		elink_pause_resolve(phy, params, vars, pause_result);  in elink_8073_resolve_fc()
8043 					     struct elink_phy *phy,  in elink_8073_8727_external_rom_boot()  argument
8052 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8058 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8063 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8068 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8074 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8094 		elink_cl45_read(sc, phy,  in elink_8073_8727_external_rom_boot()
8097 		elink_cl45_read(sc, phy,  in elink_8073_8727_external_rom_boot()
8103 			((fw_msgout & 0xff) != 0x03 && (phy->type ==  in elink_8073_8727_external_rom_boot()
8107 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8110 	elink_save_bcm_spirom_ver(sc, phy, port);  in elink_8073_8727_external_rom_boot()
8123 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)  in elink_8073_is_snr_needed()  argument
8129 	elink_cl45_read(sc, phy,  in elink_8073_is_snr_needed()
8138 	elink_cl45_read(sc, phy,  in elink_8073_is_snr_needed()
8149 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)  in elink_8073_xaui_wa()  argument
8153 	elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8168 		elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8187 				elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8205 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)  in elink_807x_force_10G()  argument
8208 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8210 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8212 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8214 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8219 				      struct elink_phy *phy,  in elink_8073_set_pause_cl37()  argument
8224 	elink_cl45_read(sc, phy,  in elink_8073_set_pause_cl37()
8229 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_8073_set_pause_cl37()
8248 	elink_cl45_write(sc, phy,  in elink_8073_set_pause_cl37()
8253 static void elink_8073_specific_func(struct elink_phy *phy,  in elink_8073_specific_func()  argument
8261 		elink_cl45_write(sc, phy,  in elink_8073_specific_func()
8263 		elink_cl45_write(sc, phy,  in elink_8073_specific_func()
8269 static elink_status_t elink_8073_config_init(struct elink_phy *phy,  in elink_8073_config_init()  argument
8289 	elink_8073_specific_func(phy, params, ELINK_PHY_INIT);  in elink_8073_config_init()
8290 	elink_8073_set_pause_cl37(params, phy, vars);  in elink_8073_config_init()
8292 	elink_cl45_read(sc, phy,  in elink_8073_config_init()
8295 	elink_cl45_read(sc, phy,  in elink_8073_config_init()
8305 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8308 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8321 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8324 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8330 		elink_807x_force_10G(sc, phy);  in elink_8073_config_init()
8334 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8337 	if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {  in elink_8073_config_init()
8338 		if (phy->req_line_speed == ELINK_SPEED_10000) {  in elink_8073_config_init()
8340 		} else if (phy->req_line_speed ==  ELINK_SPEED_2500) {  in elink_8073_config_init()
8349 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8354 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8361 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);  in elink_8073_config_init()
8362 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);  in elink_8073_config_init()
8364 	if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&  in elink_8073_config_init()
8365 	     (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||  in elink_8073_config_init()
8366 	    (phy->req_line_speed == ELINK_SPEED_2500)) {  in elink_8073_config_init()
8369 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8382 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);  in elink_8073_config_init()
8385 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);  in elink_8073_config_init()
8386 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,  in elink_8073_config_init()
8387 			 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?  in elink_8073_config_init()
8391 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in elink_8073_config_init()
8397 	if (elink_8073_is_snr_needed(sc, phy))  in elink_8073_config_init()
8398 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8403 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);  in elink_8073_config_init()
8405 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);  in elink_8073_config_init()
8407 	elink_ext_phy_set_pause(params, phy, vars);  in elink_8073_config_init()
8411 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in elink_8073_config_init()
8417 static uint8_t elink_8073_read_status(struct elink_phy *phy,  in elink_8073_read_status()  argument
8427 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8433 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8435 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8439 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8443 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8449 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8453 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8455 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8461 	     ((phy->req_line_speed != ELINK_SPEED_10000))) {  in elink_8073_read_status()
8462 		if (elink_8073_xaui_wa(sc, phy) != 0)  in elink_8073_read_status()
8465 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8467 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8471 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8473 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8479 	if (link_up && elink_8073_is_snr_needed(sc, phy)) {  in elink_8073_read_status()
8484 		elink_cl45_write(sc, phy,  in elink_8073_read_status()
8489 		elink_cl45_write(sc, phy,  in elink_8073_read_status()
8493 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8524 			elink_cl45_read(sc, phy,  in elink_8073_read_status()
8537 			elink_cl45_write(sc, phy,  in elink_8073_read_status()
8542 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_8073_read_status()
8543 		elink_8073_resolve_fc(phy, params, vars);  in elink_8073_read_status()
8548 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_8073_read_status()
8562 static void elink_8073_link_reset(struct elink_phy *phy,  in elink_8073_link_reset()  argument
8581 static elink_status_t elink_8705_config_init(struct elink_phy *phy,  in elink_8705_config_init()  argument
8592 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8705_config_init()
8593 	elink_wait_reset_complete(sc, phy, params);  in elink_8705_config_init()
8595 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8597 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8599 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8601 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8608 static uint8_t elink_8705_read_status(struct elink_phy *phy,  in elink_8705_read_status()  argument
8616 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8620 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8624 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8627 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8629 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8636 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8705_read_status()
8645 					   struct elink_phy *phy,  in elink_set_disable_pmd_transmit()  argument
8662 	elink_cl45_write(sc, phy,  in elink_set_disable_pmd_transmit()
8682 					   struct elink_phy *phy,  in elink_sfp_e1e2_set_transmitter()  argument
8700 		elink_cl45_read(sc, phy,  in elink_sfp_e1e2_set_transmitter()
8710 		elink_cl45_write(sc, phy,  in elink_sfp_e1e2_set_transmitter()
8739 				      struct elink_phy *phy,  in elink_sfp_set_transmitter()  argument
8745 		elink_sfp_e3_set_transmitter(params, phy, tx_en);  in elink_sfp_set_transmitter()
8747 		elink_sfp_e1e2_set_transmitter(params, phy, tx_en);  in elink_sfp_set_transmitter()
8750 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_8726_read_sfp_module_eeprom()  argument
8764 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8769 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8774 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8780 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8799 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8806 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8838 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_warpcore_read_sfp_module_eeprom()  argument
8881 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_8727_read_sfp_module_eeprom()  argument
8899 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8905 	elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8911 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8917 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8922 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8928 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8939 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8958 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8965 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8976 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_read_sfp_module_eeprom()  argument
8990 	switch (phy->type) {  in elink_read_sfp_module_eeprom()
9008 		rc = read_func(phy, params, dev_addr, addr, xfer_size,  in elink_read_sfp_module_eeprom()
9017 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,  in elink_get_edc_mode()  argument
9025 	phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;  in elink_get_edc_mode()
9027 	if (elink_read_sfp_module_eeprom(phy,  in elink_get_edc_mode()
9044 		phy->media_type = ELINK_ETH_PHY_DA_TWINAX;  in elink_get_edc_mode()
9052 			if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_get_edc_mode()
9086 			phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;  in elink_get_edc_mode()
9087 			if (phy->req_line_speed != ELINK_SPEED_1000) {  in elink_get_edc_mode()
9089 				phy->req_line_speed = ELINK_SPEED_1000;  in elink_get_edc_mode()
9105 				elink_sfp_set_transmitter(params, phy, 0);  in elink_get_edc_mode()
9107 				elink_sfp_set_transmitter(params, phy, 1);  in elink_get_edc_mode()
9113 				if (params->phy[idx].type == phy->type) {  in elink_get_edc_mode()
9118 			phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;  in elink_get_edc_mode()
9119 			phy->req_line_speed = params->req_line_speed[cfg_idx];  in elink_get_edc_mode()
9133 		if (&(params->phy[phy_idx]) == phy) {  in elink_get_edc_mode()
9136 			media_types |= ((phy->media_type &  in elink_get_edc_mode()
9145 		if (elink_read_sfp_module_eeprom(phy,  in elink_get_edc_mode()
9166 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,  in elink_verify_sfp_module()  argument
9174 	phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;  in elink_verify_sfp_module()
9204 	fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in elink_verify_sfp_module()
9212 	if (elink_read_sfp_module_eeprom(phy,  in elink_verify_sfp_module()
9221 	if (elink_read_sfp_module_eeprom(phy,  in elink_verify_sfp_module()
9236 		phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;  in elink_verify_sfp_module()
9240 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,  in elink_wait_for_sfp_module_initialized()  argument
9253 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_wait_for_sfp_module_initialized()
9255 				phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,  in elink_wait_for_sfp_module_initialized()
9258 			rc = elink_read_sfp_module_eeprom(phy, params,  in elink_wait_for_sfp_module_initialized()
9269 	rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,  in elink_wait_for_sfp_module_initialized()
9275 				    struct elink_phy *phy,  in elink_8727_power_module()  argument
9290 	if (phy->flags & ELINK_FLAGS_NOC)  in elink_8727_power_module()
9300 	elink_cl45_write(sc, phy,  in elink_8727_power_module()
9307 					struct elink_phy *phy,  in elink_8726_set_limiting_mode()  argument
9312 	elink_cl45_read(sc, phy,  in elink_8726_set_limiting_mode()
9321 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9335 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9339 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9343 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9347 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9356 					struct elink_phy *phy,  in elink_8727_set_limiting_mode()  argument
9361 	elink_cl45_read(sc, phy,  in elink_8727_set_limiting_mode()
9366 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9371 	elink_cl45_read(sc, phy,  in elink_8727_set_limiting_mode()
9376 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9381 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9389 static void elink_8727_specific_func(struct elink_phy *phy,  in elink_8727_specific_func()  argument
9397 		elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_specific_func()
9400 		if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))  in elink_8727_specific_func()
9401 			elink_sfp_set_transmitter(params, phy, 1);  in elink_8727_specific_func()
9404 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9407 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9410 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9413 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_specific_func()
9417 		if (phy->flags & ELINK_FLAGS_NOC)  in elink_8727_specific_func()
9422 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_specific_func()
9424 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9497 static void elink_warpcore_hw_reset(struct elink_phy *phy,  in elink_warpcore_hw_reset()  argument
9512 				   struct elink_phy *phy,  in elink_power_sfp_module()  argument
9518 	switch (phy->type) {  in elink_power_sfp_module()
9521 		elink_8727_power_module(params->sc, phy, power);  in elink_power_sfp_module()
9531 					     struct elink_phy *phy,  in elink_warpcore_set_limiting_mode()  argument
9538 	uint8_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_limiting_mode()
9540 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9558 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9561 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9565 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_set_limiting_mode()
9566 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_set_limiting_mode()
9571 				    struct elink_phy *phy,  in elink_set_limiting_mode()  argument
9574 	switch (phy->type) {  in elink_set_limiting_mode()
9576 		elink_8726_set_limiting_mode(params->sc, phy, edc_mode);  in elink_set_limiting_mode()
9580 		elink_8727_set_limiting_mode(params->sc, phy, edc_mode);  in elink_set_limiting_mode()
9583 		elink_warpcore_set_limiting_mode(params, phy, edc_mode);  in elink_set_limiting_mode()
9588 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,  in elink_sfp_module_detection()  argument
9599 	elink_sfp_set_transmitter(params, phy, 1);  in elink_sfp_module_detection()
9603 	elink_power_sfp_module(params, phy, 1);  in elink_sfp_module_detection()
9604 	if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {  in elink_sfp_module_detection()
9607 	} else if (elink_verify_sfp_module(phy, params) != 0) {  in elink_sfp_module_detection()
9619 			elink_power_sfp_module(params, phy, 0);  in elink_sfp_module_detection()
9630 	elink_set_limiting_mode(params, phy, edc_mode);  in elink_sfp_module_detection()
9638 		elink_sfp_set_transmitter(params, phy, 0);  in elink_sfp_module_detection()
9646 	struct elink_phy *phy;  in elink_handle_module_detect_int()  local
9650 		phy = &params->phy[ELINK_INT_PHY];  in elink_handle_module_detect_int()
9652 		elink_sfp_set_transmitter(params, phy, 1);  in elink_handle_module_detect_int()
9654 		phy = &params->phy[ELINK_EXT_PHY1];  in elink_handle_module_detect_int()
9672 		elink_set_aer_mmd(params, phy);  in elink_handle_module_detect_int()
9674 		elink_power_sfp_module(params, phy, 1);  in elink_handle_module_detect_int()
9678 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {  in elink_handle_module_detect_int()
9679 			elink_sfp_module_detection(phy, params);  in elink_handle_module_detect_int()
9686 				elink_cl45_read(sc, phy,  in elink_handle_module_detect_int()
9693 					elink_warpcore_reset_lane(sc, phy, 1);  in elink_handle_module_detect_int()
9694 					elink_warpcore_config_sfi(phy, params);  in elink_handle_module_detect_int()
9695 					elink_warpcore_reset_lane(sc, phy, 0);  in elink_handle_module_detect_int()
9708 		phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;  in elink_handle_module_detect_int()
9716 				 struct elink_phy *phy,  in elink_sfp_mask_fault()  argument
9721 	elink_cl45_read(sc, phy,  in elink_sfp_mask_fault()
9724 	elink_cl45_read(sc, phy,  in elink_sfp_mask_fault()
9728 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);  in elink_sfp_mask_fault()
9733 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);  in elink_sfp_mask_fault()
9738 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,  in elink_8706_8726_read_status()  argument
9747 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9750 	elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,  in elink_8706_8726_read_status()
9754 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9756 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9760 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9762 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9764 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9766 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9780 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8706_8726_read_status()
9786 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8706_8726_read_status()
9788 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8706_8726_read_status()
9800 static uint8_t elink_8706_config_init(struct elink_phy *phy,  in elink_8706_config_init()  argument
9812 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8706_config_init()
9813 	elink_wait_reset_complete(sc, phy, params);  in elink_8706_config_init()
9817 		elink_cl45_read(sc, phy,  in elink_8706_config_init()
9832 			elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);  in elink_8706_config_init()
9836 			val |= (phy->rx_preemphasis[i] & 0x7);  in elink_8706_config_init()
9839 			elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);  in elink_8706_config_init()
9843 	if (phy->req_line_speed == ELINK_SPEED_10000) {  in elink_8706_config_init()
9846 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9849 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9853 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9860 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9864 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9867 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9870 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9874 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9876 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9879 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9883 	elink_save_bcm_spirom_ver(sc, phy, params->port);  in elink_8706_config_init()
9896 		elink_cl45_read(sc, phy,  in elink_8706_config_init()
9899 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9906 static elink_status_t elink_8706_read_status(struct elink_phy *phy,  in elink_8706_read_status()  argument
9910 	return elink_8706_8726_read_status(phy, params, vars);  in elink_8706_read_status()
9916 static void elink_8726_config_loopback(struct elink_phy *phy,  in elink_8726_config_loopback()  argument
9921 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);  in elink_8726_config_loopback()
9924 static void elink_8726_external_rom_boot(struct elink_phy *phy,  in elink_8726_external_rom_boot()  argument
9932 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9936 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9941 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9945 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9954 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9959 	elink_save_bcm_spirom_ver(sc, phy, params->port);  in elink_8726_external_rom_boot()
9962 static uint8_t elink_8726_read_status(struct elink_phy *phy,  in elink_8726_read_status()  argument
9968 	uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);  in elink_8726_read_status()
9970 		elink_cl45_read(sc, phy,  in elink_8726_read_status()
9983 static elink_status_t elink_8726_config_init(struct elink_phy *phy,  in elink_8726_config_init()  argument
9990 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8726_config_init()
9991 	elink_wait_reset_complete(sc, phy, params);  in elink_8726_config_init()
9993 	elink_8726_external_rom_boot(phy, params);  in elink_8726_config_init()
10000 	elink_sfp_module_detection(phy, params);  in elink_8726_config_init()
10002 	if (phy->req_line_speed == ELINK_SPEED_1000) {  in elink_8726_config_init()
10004 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10006 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10008 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10010 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10013 	} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_8726_config_init()
10014 		   (phy->speed_cap_mask &  in elink_8726_config_init()
10016 		   ((phy->speed_cap_mask &  in elink_8726_config_init()
10021 		elink_ext_phy_set_pause(params, phy, vars);  in elink_8726_config_init()
10022 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10024 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10026 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10028 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10030 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10035 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10037 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10042 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10051 			 phy->tx_preemphasis[0],  in elink_8726_config_init()
10052 			 phy->tx_preemphasis[1]);  in elink_8726_config_init()
10053 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10056 				 phy->tx_preemphasis[0]);  in elink_8726_config_init()
10058 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10061 				 phy->tx_preemphasis[1]);  in elink_8726_config_init()
10068 static void elink_8726_link_reset(struct elink_phy *phy,  in elink_8726_link_reset()  argument
10074 	elink_cl45_write(sc, phy,  in elink_8726_link_reset()
10083 static void elink_8727_set_link_led(struct elink_phy *phy,  in elink_8727_set_link_led()  argument
10091 	if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_set_link_led()
10108 	elink_cl45_read(sc, phy,  in elink_8727_set_link_led()
10114 	elink_cl45_write(sc, phy,  in elink_8727_set_link_led()
10118 	elink_cl45_read(sc, phy,  in elink_8727_set_link_led()
10124 	elink_cl45_write(sc, phy,  in elink_8727_set_link_led()
10129 static void elink_8727_hw_reset(struct elink_phy *phy,  in elink_8727_hw_reset()  argument
10144 static void elink_8727_config_speed(struct elink_phy *phy,  in elink_8727_config_speed()  argument
10150 	if ((phy->req_line_speed == ELINK_SPEED_1000) ||  in elink_8727_config_speed()
10151 	    (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {  in elink_8727_config_speed()
10153 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10155 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10157 		elink_cl45_read(sc, phy,  in elink_8727_config_speed()
10164 			elink_cl45_read(sc, phy,  in elink_8727_config_speed()
10168 			elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10172 	} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_8727_config_speed()
10173 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10175 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10180 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10182 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10188 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10191 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10193 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10195 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10201 static elink_status_t elink_8727_config_init(struct elink_phy *phy,  in elink_8727_config_init()  argument
10210 	elink_wait_reset_complete(sc, phy, params);  in elink_8727_config_init()
10214 	elink_8727_specific_func(phy, params, ELINK_PHY_INIT);  in elink_8727_config_init()
10218 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10225 	if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_config_init()
10227 	elink_cl45_write(sc, phy,  in elink_8727_config_init()
10231 	elink_set_disable_pmd_transmit(params, phy, 0);  in elink_8727_config_init()
10233 	elink_8727_power_module(sc, phy, 1);  in elink_8727_config_init()
10235 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10238 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10241 	elink_8727_config_speed(phy, params);  in elink_8727_config_init()
10248 			   phy->tx_preemphasis[0],  in elink_8727_config_init()
10249 			   phy->tx_preemphasis[1]);  in elink_8727_config_init()
10250 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10252 				 phy->tx_preemphasis[0]);  in elink_8727_config_init()
10254 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10256 				 phy->tx_preemphasis[1]);  in elink_8727_config_init()
10270 		elink_cl45_read(sc, phy,  in elink_8727_config_init()
10274 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10276 		elink_cl45_read(sc, phy,  in elink_8727_config_init()
10279 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10287 static void elink_8727_handle_mod_abs(struct elink_phy *phy,  in elink_8727_handle_mod_abs()  argument
10296 	elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10304 		phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;  in elink_8727_handle_mod_abs()
10313 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_handle_mod_abs()
10315 		elink_cl45_write(sc, phy,  in elink_8727_handle_mod_abs()
10322 		elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10338 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_handle_mod_abs()
10340 		elink_cl45_write(sc, phy,  in elink_8727_handle_mod_abs()
10349 		elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10356 			elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_handle_mod_abs()
10358 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0)  in elink_8727_handle_mod_abs()
10359 			elink_sfp_module_detection(phy, params);  in elink_8727_handle_mod_abs()
10364 		elink_8727_config_speed(phy, params);  in elink_8727_handle_mod_abs()
10372 static uint8_t elink_8727_read_status(struct elink_phy *phy,  in elink_8727_read_status()  argument
10383 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10390 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10396 	elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,  in elink_8727_read_status()
10399 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10405 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10411 	if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {  in elink_8727_read_status()
10413 		elink_cl45_read(sc, phy,  in elink_8727_read_status()
10432 			elink_cl45_write(sc, phy,  in elink_8727_read_status()
10436 			elink_cl45_read(sc, phy,  in elink_8727_read_status()
10441 			elink_cl45_write(sc, phy,  in elink_8727_read_status()
10445 			elink_cl45_read(sc, phy,  in elink_8727_read_status()
10448 			elink_8727_power_module(params->sc, phy, 0);  in elink_8727_read_status()
10455 		elink_8727_handle_mod_abs(phy, params);  in elink_8727_read_status()
10457 		elink_cl45_write(sc, phy,  in elink_8727_read_status()
10462 	if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {  in elink_8727_read_status()
10464 		elink_sfp_set_transmitter(params, phy, 1);  in elink_8727_read_status()
10470 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10495 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_read_status()
10498 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_read_status()
10507 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8727_read_status()
10513 	    (phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_8727_read_status()
10514 		elink_cl45_read(sc, phy,  in elink_8727_read_status()
10524 		elink_cl45_write(sc, phy,  in elink_8727_read_status()
10531 static void elink_8727_link_reset(struct elink_phy *phy,  in elink_8727_link_reset()  argument
10537 	elink_set_disable_pmd_transmit(params, phy, 1);  in elink_8727_link_reset()
10540 	elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_link_reset()
10542 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);  in elink_8727_link_reset()
10549 static int elink_is_8483x_8485x(struct elink_phy *phy)  in elink_is_8483x_8485x()  argument
10551 	return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||  in elink_is_8483x_8485x()
10552 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||  in elink_is_8483x_8485x()
10553 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));  in elink_is_8483x_8485x()
10556 static void elink_save_848xx_spirom_version(struct elink_phy *phy,  in elink_save_848xx_spirom_version()  argument
10570 	if (elink_is_8483x_8485x(phy)) {  in elink_save_848xx_spirom_version()
10571 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);  in elink_save_848xx_spirom_version()
10573 				phy->ver_addr);  in elink_save_848xx_spirom_version()
10578 			elink_cl45_write(sc, phy, reg_set[i].devad,  in elink_save_848xx_spirom_version()
10582 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10591 						  phy->ver_addr);  in elink_save_848xx_spirom_version()
10597 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);  in elink_save_848xx_spirom_version()
10598 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);  in elink_save_848xx_spirom_version()
10599 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);  in elink_save_848xx_spirom_version()
10601 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10610 						  phy->ver_addr);  in elink_save_848xx_spirom_version()
10615 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);  in elink_save_848xx_spirom_version()
10617 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);  in elink_save_848xx_spirom_version()
10620 					  phy->ver_addr);  in elink_save_848xx_spirom_version()
10625 				struct elink_phy *phy)  in elink_848xx_set_led()  argument
10638 	elink_cl45_read(sc, phy,  in elink_848xx_set_led()
10644 	elink_cl45_write(sc, phy,  in elink_848xx_set_led()
10649 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_848xx_set_led()
10652 	if (elink_is_8483x_8485x(phy))  in elink_848xx_set_led()
10658 	elink_cl45_read_or_write(sc, phy,  in elink_848xx_set_led()
10663 static void elink_848xx_specific_func(struct elink_phy *phy,  in elink_848xx_specific_func()  argument
10670 		if (!elink_is_8483x_8485x(phy)) {  in elink_848xx_specific_func()
10672 			elink_save_848xx_spirom_version(phy, sc, params->port);  in elink_848xx_specific_func()
10681 		elink_848xx_set_led(sc, phy);  in elink_848xx_specific_func()
10686 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,  in elink_848xx_cmn_config_init()  argument
10693 	elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);  in elink_848xx_cmn_config_init()
10694 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10698 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10702 	elink_ext_phy_set_pause(params, phy, vars);  in elink_848xx_cmn_config_init()
10703 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10707 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10714 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_848xx_cmn_config_init()
10715 	     (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10717 	    (phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_848xx_cmn_config_init()
10720 		if (phy->req_duplex == DUPLEX_FULL)  in elink_848xx_cmn_config_init()
10726 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10731 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_848xx_cmn_config_init()
10732 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10741 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10750 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10752 		    (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {  in elink_848xx_cmn_config_init()
10758 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10760 		    (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {  in elink_848xx_cmn_config_init()
10768 	if ((phy->req_line_speed == ELINK_SPEED_100) &&  in elink_848xx_cmn_config_init()
10769 	    (phy->supported &  in elink_848xx_cmn_config_init()
10774 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10781 	if ((phy->req_line_speed == ELINK_SPEED_10) &&  in elink_848xx_cmn_config_init()
10782 	    (phy->supported &  in elink_848xx_cmn_config_init()
10786 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10792 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10796 	if (phy->req_duplex == DUPLEX_FULL)  in elink_848xx_cmn_config_init()
10802 	if (!elink_is_8483x_8485x(phy) ||  in elink_848xx_cmn_config_init()
10804 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10808 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_848xx_cmn_config_init()
10809 	    (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10811 		(phy->req_line_speed == ELINK_SPEED_10000)) {  in elink_848xx_cmn_config_init()
10816 				sc, phy,  in elink_848xx_cmn_config_init()
10820 			elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10824 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10832 static elink_status_t elink_8481_config_init(struct elink_phy *phy,  in elink_8481_config_init()  argument
10843 	elink_wait_reset_complete(sc, phy, params);  in elink_8481_config_init()
10845 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8481_config_init()
10846 	return elink_848xx_cmn_config_init(phy, params, vars);  in elink_8481_config_init()
10852 static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,  in elink_84858_cmd_hdlr()  argument
10869 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10886 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10894 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10903 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10921 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10929 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,  in elink_84833_cmd_hdlr()  argument
10940 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10946 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10959 			elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10969 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10976 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10979 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10994 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
11001 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
11008 static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,  in elink_848xx_cmd_hdlr()  argument
11016 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||  in elink_848xx_cmd_hdlr()
11020 		return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in elink_848xx_cmd_hdlr()
11023 		return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in elink_848xx_cmd_hdlr()
11028 static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,  in elink_848xx_pair_swap_cfg()  argument
11049 	status = elink_848xx_cmd_hdlr(phy, params,  in elink_848xx_pair_swap_cfg()
11096 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,  in elink_84833_hw_reset_phy()  argument
11108 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_84833_hw_reset_phy()
11111 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_84833_hw_reset_phy()
11129 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,  in elink_8483x_disable_eee()  argument
11140 	rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in elink_8483x_disable_eee()
11147 	return elink_eee_disable(phy, params, vars);  in elink_8483x_disable_eee()
11150 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,  in elink_8483x_enable_eee()  argument
11158 	rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in elink_8483x_enable_eee()
11165 	return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);  in elink_8483x_enable_eee()
11169 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,  in elink_848x3_config_init()  argument
11187 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_config_init()
11193 		elink_cl45_write(sc, phy,  in elink_848x3_config_init()
11198 	elink_wait_reset_complete(sc, phy, params);  in elink_848x3_config_init()
11202 	if (!elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11209 		elink_set_autoneg(&params->phy[ELINK_INT_PHY], params, vars, 0);  in elink_848x3_config_init()
11210 		elink_program_serdes(&params->phy[ELINK_INT_PHY], params, vars);  in elink_848x3_config_init()
11214 	if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {  in elink_848x3_config_init()
11217 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848x3_config_init()
11226 	elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11262 	if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)  in elink_848x3_config_init()
11265 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11270 	if (elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11271 		elink_848xx_pair_swap_cfg(phy, params, vars);  in elink_848x3_config_init()
11278 		rc = elink_848xx_cmd_hdlr(phy, params,  in elink_848x3_config_init()
11285 		rc = elink_848xx_cmn_config_init(phy, params, vars);  in elink_848x3_config_init()
11287 		elink_save_848xx_spirom_version(phy, sc, params->port);  in elink_848x3_config_init()
11289 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_config_init()
11295 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11301 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11305 	elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11315 			elink_8483x_disable_eee(phy, params, vars);  in elink_848x3_config_init()
11319 		if ((phy->req_duplex == DUPLEX_FULL) &&  in elink_848x3_config_init()
11323 			rc = elink_8483x_enable_eee(phy, params, vars);  in elink_848x3_config_init()
11325 			rc = elink_8483x_disable_eee(phy, params, vars);  in elink_848x3_config_init()
11334 	if (elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11336 		elink_cl45_read_and_write(sc, phy,  in elink_848x3_config_init()
11344 static uint8_t elink_848xx_read_status(struct elink_phy *phy,  in elink_848xx_read_status()  argument
11355 	elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11357 	elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11367 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_848xx_read_status()
11372 		elink_cl45_write(sc, phy,  in elink_848xx_read_status()
11377 		elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11401 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11420 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11427 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11439 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_848xx_read_status()
11442 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11460 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11470 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11478 		if (elink_is_8483x_8485x(phy))  in elink_848xx_read_status()
11479 			elink_eee_an_resolve(phy, params, vars);  in elink_848xx_read_status()
11494 static void elink_8481_hw_reset(struct elink_phy *phy,  in elink_8481_hw_reset()  argument
11503 static void elink_8481_link_reset(struct elink_phy *phy,  in elink_8481_link_reset()  argument
11506 	elink_cl45_write(params->sc, phy,  in elink_8481_link_reset()
11508 	elink_cl45_write(params->sc, phy,  in elink_8481_link_reset()
11512 static void elink_848x3_link_reset(struct elink_phy *phy,  in elink_848x3_link_reset()  argument
11524 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_link_reset()
11529 		elink_cl45_read(sc, phy,  in elink_848x3_link_reset()
11533 		elink_cl45_write(sc, phy,  in elink_848x3_link_reset()
11539 static void elink_848xx_set_link_led(struct elink_phy *phy,  in elink_848xx_set_link_led()  argument
11559 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11564 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11569 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11574 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11580 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11595 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11600 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11605 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11610 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11616 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11620 			if (phy->type ==  in elink_848xx_set_link_led()
11637 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11651 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11658 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11664 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11669 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11674 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11679 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11684 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11688 			if (phy->type ==  in elink_848xx_set_link_led()
11705 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11721 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11730 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11737 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11742 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11747 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11752 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11766 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11772 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11778 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11782 			if (phy->type ==  in elink_848xx_set_link_led()
11787 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11806 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_848xx_set_link_led()
11814 static void elink_54618se_specific_func(struct elink_phy *phy,  in elink_54618se_specific_func()  argument
11824 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11827 		elink_cl22_read(sc, phy,  in elink_54618se_specific_func()
11832 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11836 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11843 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,  in elink_54618se_config_init()  argument
11873 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11875 	elink_wait_reset_complete(sc, phy, params);  in elink_54618se_config_init()
11881 	elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);  in elink_54618se_config_init()
11883 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11886 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11890 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11896 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_54618se_config_init()
11907 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11911 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11915 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11924 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_54618se_config_init()
11925 			(phy->speed_cap_mask &  in elink_54618se_config_init()
11927 			(phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_54618se_config_init()
11930 		if (phy->req_duplex == DUPLEX_FULL)  in elink_54618se_config_init()
11936 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11939 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11944 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_54618se_config_init()
11945 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11951 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11957 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11963 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11972 	if (phy->req_line_speed == ELINK_SPEED_100) {  in elink_54618se_config_init()
11975 		elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11980 	if (phy->req_line_speed == ELINK_SPEED_10) {  in elink_54618se_config_init()
11982 		elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11988 	if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {  in elink_54618se_config_init()
11991 		elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,  in elink_54618se_config_init()
11994 		elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);  in elink_54618se_config_init()
11996 		elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);  in elink_54618se_config_init()
12001 			elink_eee_disable(phy, params, vars);  in elink_54618se_config_init()
12003 			   (phy->req_duplex == DUPLEX_FULL) &&  in elink_54618se_config_init()
12011 			elink_eee_advertise(phy, params, vars,  in elink_54618se_config_init()
12015 			elink_eee_disable(phy, params, vars);  in elink_54618se_config_init()
12021 		if (phy->flags & ELINK_FLAGS_EEE) {  in elink_54618se_config_init()
12031 			elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_54618se_config_init()
12036 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
12040 	if (phy->req_duplex == DUPLEX_FULL)  in elink_54618se_config_init()
12043 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
12050 static void elink_5461x_set_link_led(struct elink_phy *phy,  in elink_5461x_set_link_led()  argument
12056 	elink_cl22_write(sc, phy,  in elink_5461x_set_link_led()
12059 	elink_cl22_read(sc, phy,  in elink_5461x_set_link_led()
12079 	elink_cl22_write(sc, phy,  in elink_5461x_set_link_led()
12086 static void elink_54618se_link_reset(struct elink_phy *phy,  in elink_54618se_link_reset()  argument
12096 	elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);  in elink_54618se_link_reset()
12111 static uint8_t elink_54618se_read_status(struct elink_phy *phy,  in elink_54618se_read_status()  argument
12121 	elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12127 	elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12164 		elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12170 		elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12180 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_54618se_read_status()
12184 			elink_cl22_read(sc, phy, 0x5, &val);  in elink_54618se_read_status()
12202 			elink_cl22_read(sc, phy, 0xa, &val);  in elink_54618se_read_status()
12210 			if ((phy->flags & ELINK_FLAGS_EEE) &&  in elink_54618se_read_status()
12212 				elink_eee_an_resolve(phy, params, vars);  in elink_54618se_read_status()
12218 static void elink_54618se_config_loopback(struct elink_phy *phy,  in elink_54618se_config_loopback()  argument
12229 	elink_cl22_write(sc, phy, 0x09, 3<<11);  in elink_54618se_config_loopback()
12236 	elink_cl22_read(sc, phy, 0x00, &val);  in elink_54618se_config_loopback()
12239 	elink_cl22_write(sc, phy, 0x00, val);  in elink_54618se_config_loopback()
12245 	elink_cl22_write(sc, phy, 0x18, 7);  in elink_54618se_config_loopback()
12246 	elink_cl22_read(sc, phy, 0x18, &val);  in elink_54618se_config_loopback()
12247 	elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));  in elink_54618se_config_loopback()
12261 static void elink_7101_config_loopback(struct elink_phy *phy,  in elink_7101_config_loopback()  argument
12266 	elink_cl45_write(sc, phy,  in elink_7101_config_loopback()
12270 static elink_status_t elink_7101_config_init(struct elink_phy *phy,  in elink_7101_config_init()  argument
12283 	elink_wait_reset_complete(sc, phy, params);  in elink_7101_config_init()
12285 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12288 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12291 	elink_ext_phy_set_pause(params, phy, vars);  in elink_7101_config_init()
12293 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12296 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12300 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12303 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12306 				  (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);  in elink_7101_config_init()
12310 static uint8_t elink_7101_read_status(struct elink_phy *phy,  in elink_7101_read_status()  argument
12317 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12319 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12323 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12325 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12332 		elink_cl45_read(sc, phy,  in elink_7101_read_status()
12339 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_7101_read_status()
12340 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_7101_read_status()
12363 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)  in elink_sfx7101_sp_sw_reset()  argument
12367 	elink_cl45_read(sc, phy,  in elink_sfx7101_sp_sw_reset()
12374 		elink_cl45_write(sc, phy,  in elink_sfx7101_sp_sw_reset()
12379 		elink_cl45_read(sc, phy,  in elink_sfx7101_sp_sw_reset()
12388 static void elink_7101_hw_reset(struct elink_phy *phy,  in elink_7101_hw_reset()  argument
12398 static void elink_7101_set_link_led(struct elink_phy *phy,  in elink_7101_set_link_led()  argument
12415 	elink_cl45_write(sc, phy,  in elink_7101_set_link_led()
12959 				     struct elink_phy *phy, uint8_t port,  in elink_populate_preemphasis()  argument
12987 		phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);  in elink_populate_preemphasis()
12988 		phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);  in elink_populate_preemphasis()
12990 		phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);  in elink_populate_preemphasis()
12991 		phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);  in elink_populate_preemphasis()
12993 			phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]);  in elink_populate_preemphasis()
13020 				  struct elink_phy *phy)  in elink_populate_int_phy()  argument
13036 		*phy = phy_warpcore;  in elink_populate_int_phy()
13038 			phy->flags |= ELINK_FLAGS_4_PORT_MODE;  in elink_populate_int_phy()
13040 			phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;  in elink_populate_int_phy()
13051 			phy->supported &= (ELINK_SUPPORTED_10baseT_Half |  in elink_populate_int_phy()
13060 			phy->media_type = ELINK_ETH_PHY_BASE_T;  in elink_populate_int_phy()
13063 			phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |  in elink_populate_int_phy()
13068 			phy->media_type = ELINK_ETH_PHY_XFP_FIBER;  in elink_populate_int_phy()
13071 			phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |  in elink_populate_int_phy()
13076 			phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;  in elink_populate_int_phy()
13079 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13080 			phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |  in elink_populate_int_phy()
13088 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13089 			phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;  in elink_populate_int_phy()
13090 			phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |  in elink_populate_int_phy()
13096 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13097 			phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;  in elink_populate_int_phy()
13098 			phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |  in elink_populate_int_phy()
13105 			phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;  in elink_populate_int_phy()
13118 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;  in elink_populate_int_phy()
13120 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;  in elink_populate_int_phy()
13122 				phy->media_type, phy->flags, phy->supported);  in elink_populate_int_phy()
13130 			*phy = phy_serdes;  in elink_populate_int_phy()
13136 			*phy = phy_xgxs;  in elink_populate_int_phy()
13143 	phy->addr = (uint8_t)phy_addr;  in elink_populate_int_phy()
13144 	phy->mdio_ctrl = elink_get_emac_base(sc,  in elink_populate_int_phy()
13148 		phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;  in elink_populate_int_phy()
13150 		phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;  in elink_populate_int_phy()
13153 		   port, phy->addr, phy->mdio_ctrl);  in elink_populate_int_phy()
13155 	elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);  in elink_populate_int_phy()
13164 				  struct elink_phy *phy)  in elink_populate_ext_phy()  argument
13175 		*phy = phy_8073;  in elink_populate_ext_phy()
13178 		*phy = phy_8705;  in elink_populate_ext_phy()
13181 		*phy = phy_8706;  in elink_populate_ext_phy()
13185 		*phy = phy_8726;  in elink_populate_ext_phy()
13190 		*phy = phy_8727;  in elink_populate_ext_phy()
13191 		phy->flags |= ELINK_FLAGS_NOC;  in elink_populate_ext_phy()
13196 		*phy = phy_8727;  in elink_populate_ext_phy()
13199 		*phy = phy_8481;  in elink_populate_ext_phy()
13202 		*phy = phy_84823;  in elink_populate_ext_phy()
13205 		*phy = phy_84833;  in elink_populate_ext_phy()
13208 		*phy = phy_84834;  in elink_populate_ext_phy()
13211 		*phy = phy_84858;  in elink_populate_ext_phy()
13215 		*phy = phy_54618se;  in elink_populate_ext_phy()
13217 			phy->flags |= ELINK_FLAGS_EEE;  in elink_populate_ext_phy()
13220 		*phy = phy_7101;  in elink_populate_ext_phy()
13223 		*phy = phy_null;  in elink_populate_ext_phy()
13226 		*phy = phy_null;  in elink_populate_ext_phy()
13234 	phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);  in elink_populate_ext_phy()
13235 	elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);  in elink_populate_ext_phy()
13244 		phy->ver_addr = shmem_base + offsetof(struct shmem_region,  in elink_populate_ext_phy()
13256 			phy->ver_addr = shmem2_base +  in elink_populate_ext_phy()
13267 	phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);  in elink_populate_ext_phy()
13269 	if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {  in elink_populate_ext_phy()
13273 		uint32_t raw_ver = REG_RD(sc, phy->ver_addr);  in elink_populate_ext_phy()
13276 			phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |  in elink_populate_ext_phy()
13283 		   phy->addr, phy->mdio_ctrl);  in elink_populate_ext_phy()
13288 			      uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)  in elink_populate_phy()  argument
13291 	phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;  in elink_populate_phy()
13293 		return elink_populate_int_phy(sc, shmem_base, port, phy);  in elink_populate_phy()
13295 					port, phy);  in elink_populate_phy()
13300 			      struct elink_phy *phy,  in elink_phy_def_cfg()  argument
13310 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13318 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13325 	   phy_index, link_config, phy->speed_cap_mask);  in elink_phy_def_cfg()
13327 	phy->req_duplex = DUPLEX_FULL;  in elink_phy_def_cfg()
13330 		phy->req_duplex = DUPLEX_HALF;  in elink_phy_def_cfg()
13332 		phy->req_line_speed = ELINK_SPEED_10;  in elink_phy_def_cfg()
13335 		phy->req_duplex = DUPLEX_HALF;  in elink_phy_def_cfg()
13337 		phy->req_line_speed = ELINK_SPEED_100;  in elink_phy_def_cfg()
13340 		phy->req_line_speed = ELINK_SPEED_1000;  in elink_phy_def_cfg()
13343 		phy->req_line_speed = ELINK_SPEED_2500;  in elink_phy_def_cfg()
13346 		phy->req_line_speed = ELINK_SPEED_10000;  in elink_phy_def_cfg()
13349 		phy->req_line_speed = ELINK_SPEED_AUTO_NEG;  in elink_phy_def_cfg()
13354 			phy_index, phy->req_duplex);  in elink_phy_def_cfg()
13358 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;  in elink_phy_def_cfg()
13361 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;  in elink_phy_def_cfg()
13364 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;  in elink_phy_def_cfg()
13367 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;  in elink_phy_def_cfg()
13370 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;  in elink_phy_def_cfg()
13374 			phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl);  in elink_phy_def_cfg()
13414 	struct elink_phy *phy;  in elink_phy_probe()  local
13436 		phy = &params->phy[actual_phy_idx];  in elink_phy_probe()
13439 				       phy) != ELINK_STATUS_OK) {  in elink_phy_probe()
13446 				*phy = phy_null;  in elink_phy_probe()
13449 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)  in elink_phy_probe()
13454 			phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;  in elink_phy_probe()
13458 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;  in elink_phy_probe()
13472 			media_types |= ((phy->media_type &  in elink_phy_probe()
13479 		elink_phy_def_cfg(params, phy, phy_index);  in elink_phy_probe()
13726 	elink_set_aer_mmd(params, &params->phy[0]);  in elink_init_xmac_loopback()
13727 	elink_warpcore_reset_lane(sc, &params->phy[0], 0);  in elink_init_xmac_loopback()
13728 	params->phy[ELINK_INT_PHY].config_loopback(  in elink_init_xmac_loopback()
13729 			&params->phy[ELINK_INT_PHY],  in elink_init_xmac_loopback()
13755 	struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];  in elink_init_xgxs_loopback()
13793 			if (params->phy[phy_index].config_loopback)  in elink_init_xgxs_loopback()
13794 				params->phy[phy_index].config_loopback(  in elink_init_xgxs_loopback()
13795 					&params->phy[phy_index],  in elink_init_xgxs_loopback()
13838 		struct elink_phy *phy = &params->phy[phy_idx];  in elink_avoid_link_flap()  local
13839 		if (phy->phy_specific_func) {  in elink_avoid_link_flap()
13841 			phy->phy_specific_func(phy, params, ELINK_PHY_INIT);  in elink_avoid_link_flap()
13843 		if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||  in elink_avoid_link_flap()
13844 		    (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||  in elink_avoid_link_flap()
13845 		    (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))  in elink_avoid_link_flap()
13846 			elink_verify_sfp_module(phy, params);  in elink_avoid_link_flap()
14132 			if (params->phy[phy_index].link_reset) {  in elink_link_reset()
14134 						  &params->phy[phy_index]);  in elink_link_reset()
14135 				params->phy[phy_index].link_reset(  in elink_link_reset()
14136 					&params->phy[phy_index],  in elink_link_reset()
14139 			if (params->phy[phy_index].flags &  in elink_link_reset()
14154 	if (params->phy[ELINK_INT_PHY].link_reset)  in elink_link_reset()
14155 		params->phy[ELINK_INT_PHY].link_reset(  in elink_link_reset()
14156 			&params->phy[ELINK_INT_PHY], params);  in elink_link_reset()
14237 	struct elink_phy phy[PORT_MAX];  in elink_8073_common_init_phy()  local
14263 				       port_of_path, &phy[port]) !=  in elink_8073_common_init_phy()
14284 		elink_cl45_write(sc, &phy[port],  in elink_8073_common_init_phy()
14293 	if (phy[PORT_0].addr & 0x1) {  in elink_8073_common_init_phy()
14294 		phy_blk[PORT_0] = &(phy[PORT_1]);  in elink_8073_common_init_phy()
14295 		phy_blk[PORT_1] = &(phy[PORT_0]);  in elink_8073_common_init_phy()
14297 		phy_blk[PORT_0] = &(phy[PORT_0]);  in elink_8073_common_init_phy()
14298 		phy_blk[PORT_1] = &(phy[PORT_1]);  in elink_8073_common_init_phy()
14365 	struct elink_phy phy;  in elink_8726_common_init_phy()  local
14388 				       port, &phy) !=  in elink_8726_common_init_phy()
14395 		elink_cl45_write(sc, &phy,  in elink_8726_common_init_phy()
14460 	struct elink_phy phy[PORT_MAX];  in elink_8727_common_init_phy()  local
14504 				       port_of_path, &phy[port]) !=  in elink_8727_common_init_phy()
14519 		elink_cl45_write(sc, &phy[port],  in elink_8727_common_init_phy()
14525 	if (phy[PORT_0].addr & 0x1) {  in elink_8727_common_init_phy()
14526 		phy_blk[PORT_0] = &(phy[PORT_1]);  in elink_8727_common_init_phy()
14527 		phy_blk[PORT_1] = &(phy[PORT_0]);  in elink_8727_common_init_phy()
14529 		phy_blk[PORT_0] = &(phy[PORT_0]);  in elink_8727_common_init_phy()
14530 		phy_blk[PORT_1] = &(phy[PORT_1]);  in elink_8727_common_init_phy()
14838 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,  in elink_sfp_tx_fault_detection()  argument
14874 		if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {  in elink_sfp_tx_fault_detection()
14883 			       struct elink_phy *phy)  in elink_kr2_recovery()  argument
14887 	elink_warpcore_enable_AN_KR2(phy, params, vars);  in elink_kr2_recovery()
14888 	elink_warpcore_restart_AN_KR(phy, params);  in elink_kr2_recovery()
14893 			       struct elink_phy *phy)  in elink_check_kr2_wa()  argument
14909 	sigdet = elink_warpcore_get_sigdet(phy, params);  in elink_check_kr2_wa()
14912 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14918 	lane = elink_get_warpcore_lane(phy, params);  in elink_check_kr2_wa()
14919 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_check_kr2_wa()
14921 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_check_kr2_wa()
14923 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_check_kr2_wa()
14925 	elink_set_aer_mmd(params, phy);  in elink_check_kr2_wa()
14930 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14949 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14957 		elink_disable_kr2(params, vars, phy);  in elink_check_kr2_wa()
14959 		elink_warpcore_restart_AN_KR(phy, params);  in elink_check_kr2_wa()
14969 		if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {  in elink_period_func()
14970 			elink_set_aer_mmd(params, &params->phy[phy_idx]);  in elink_period_func()
14979 		struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_period_func()  local
14980 		elink_set_aer_mmd(params, phy);  in elink_period_func()
14981 		if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_period_func()
14982 		     (phy->speed_cap_mask &  in elink_period_func()
14984 		    (phy->req_line_speed == ELINK_SPEED_20000))  in elink_period_func()
14985 			elink_check_kr2_wa(params, vars, phy);  in elink_period_func()
14988 			elink_warpcore_config_runtime(phy, params, vars);  in elink_period_func()
14995 			if (elink_is_sfp_module_plugged(phy, params)) {  in elink_period_func()
14996 				elink_sfp_tx_fault_detection(phy, params, vars);  in elink_period_func()
15015 	struct elink_phy phy;  in elink_fan_failure_det_req()  local
15019 				       port, &phy)  in elink_fan_failure_det_req()
15024 		fan_failure_det_req |= (phy.flags &  in elink_fan_failure_det_req()
15043 		if (params->phy[phy_index].hw_reset) {  in elink_hw_reset_phy()
15044 			params->phy[phy_index].hw_reset(  in elink_hw_reset_phy()
15045 				&params->phy[phy_index],  in elink_hw_reset_phy()
15047 			params->phy[phy_index] = phy_null;  in elink_hw_reset_phy()
15067 		struct elink_phy phy;  in elink_init_mod_abs_int()  local
15071 					       shmem2_base, port, &phy)  in elink_init_mod_abs_int()
15076 			if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {  in elink_init_mod_abs_int()