Lines Matching refs:MDIO_WC_DEVAD
582 #define MDIO_WC_DEVAD 0x3 macro
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, in elink_warpcore_enable_AN_KR2()
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, in elink_warpcore_enable_AN_KR2()
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, in elink_warpcore_enable_AN_KR2()
4474 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, in elink_warpcore_enable_AN_KR2()
4475 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, in elink_warpcore_enable_AN_KR2()
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, in elink_warpcore_enable_AN_KR2()
4478 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, in elink_warpcore_enable_AN_KR2()
4479 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, in elink_warpcore_enable_AN_KR2()
4480 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, in elink_warpcore_enable_AN_KR2()
4481 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, in elink_warpcore_enable_AN_KR2()
4482 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, in elink_warpcore_enable_AN_KR2()
4483 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, in elink_warpcore_enable_AN_KR2()
4484 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, in elink_warpcore_enable_AN_KR2()
4485 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, in elink_warpcore_enable_AN_KR2()
4486 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} in elink_warpcore_enable_AN_KR2()
4490 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR2()
4510 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, in elink_disable_kr2()
4511 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, in elink_disable_kr2()
4512 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, in elink_disable_kr2()
4513 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, in elink_disable_kr2()
4514 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, in elink_disable_kr2()
4515 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, in elink_disable_kr2()
4516 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, in elink_disable_kr2()
4517 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, in elink_disable_kr2()
4518 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, in elink_disable_kr2()
4519 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, in elink_disable_kr2()
4520 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, in elink_disable_kr2()
4521 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, in elink_disable_kr2()
4522 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, in elink_disable_kr2()
4523 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, in elink_disable_kr2()
4524 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} in elink_disable_kr2()
4543 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_lpi_passthrough()
4545 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_lpi_passthrough()
4571 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in elink_warpcore_enable_AN_KR()
4573 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, in elink_warpcore_enable_AN_KR()
4574 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, in elink_warpcore_enable_AN_KR()
4578 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, in elink_warpcore_enable_AN_KR()
4586 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4590 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4601 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); in elink_warpcore_enable_AN_KR()
4621 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4626 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4632 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4651 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4660 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4664 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4674 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4678 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4685 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4690 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4705 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4724 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in elink_warpcore_set_10G_KR()
4725 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, in elink_warpcore_set_10G_KR()
4729 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, in elink_warpcore_set_10G_KR()
4730 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, in elink_warpcore_set_10G_KR()
4744 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4747 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4750 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4753 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4765 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4769 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4773 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4777 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4779 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4793 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4797 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4804 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4808 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4812 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4816 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4821 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4823 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4828 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4884 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4892 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4897 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4901 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4907 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4911 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4915 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4929 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4939 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4943 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4947 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4950 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4953 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4957 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4959 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4966 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4977 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4981 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4984 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4987 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4990 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4993 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4996 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4999 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5002 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5005 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5009 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5013 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5017 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5021 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5035 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5042 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5047 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5068 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5073 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5079 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5086 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5091 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5093 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5098 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5103 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5115 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5121 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5123 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5136 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, in elink_warpcore_clear_regs()
5137 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, in elink_warpcore_clear_regs()
5138 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, in elink_warpcore_clear_regs()
5139 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, in elink_warpcore_clear_regs()
5141 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, in elink_warpcore_clear_regs()
5143 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, in elink_warpcore_clear_regs()
5145 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, in elink_warpcore_clear_regs()
5146 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, in elink_warpcore_clear_regs()
5147 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, in elink_warpcore_clear_regs()
5148 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} in elink_warpcore_clear_regs()
5151 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_clear_regs()
5159 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_clear_regs()
5229 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in elink_warpcore_get_sigdet()
5258 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, in elink_warpcore_config_runtime()
5447 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5450 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5457 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5461 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5465 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5470 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5473 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5482 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5506 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5511 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5516 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5524 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5527 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
6551 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6553 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6563 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6571 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6594 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6602 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6635 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6651 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6654 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
7340 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
7342 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
7348 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
9540 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9558 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9687 MDIO_WC_DEVAD, in elink_handle_module_detect_int()
11806 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_848xx_set_link_led()