Lines Matching refs:MDIO_AN_DEVAD
454 #define MDIO_AN_DEVAD 0x7 macro
3790 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in elink_eee_disable()
3816 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in elink_eee_advertise()
3843 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in elink_eee_an_resolve()
3844 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in elink_eee_an_resolve()
4292 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in elink_ext_phy_set_pause()
4309 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in elink_ext_phy_set_pause()
4375 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, in elink_ext_phy_update_adv_fc()
4381 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4383 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4386 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4388 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4399 MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4402 MDIO_AN_DEVAD, in elink_ext_phy_update_adv_fc()
4557 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_restart_AN_KR()
4576 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, in elink_warpcore_enable_AN_KR()
4613 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_enable_AN_KR()
4637 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_enable_AN_KR()
4641 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_enable_AN_KR()
4727 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, in elink_warpcore_set_10G_KR()
4728 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, in elink_warpcore_set_10G_KR()
4801 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in elink_warpcore_set_10G_XFI()
4936 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_set_20G_force_KR2()
5135 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, in elink_warpcore_clear_regs()
5272 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_config_runtime()
6582 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_read_status()
6584 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_read_status()
6623 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_warpcore_read_status()
7995 MDIO_AN_DEVAD, in elink_ext_phy_10G_an_resolve()
7998 MDIO_AN_DEVAD, in elink_ext_phy_10G_an_resolve()
8026 MDIO_AN_DEVAD, in elink_8073_resolve_fc()
8030 MDIO_AN_DEVAD, in elink_8073_resolve_fc()
8215 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in elink_807x_force_10G()
8225 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); in elink_8073_set_pause_cl37()
8249 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); in elink_8073_set_pause_cl37()
8322 MDIO_AN_DEVAD, in elink_8073_config_init()
8325 MDIO_AN_DEVAD, in elink_8073_config_init()
8361 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in elink_8073_config_init()
8362 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in elink_8073_config_init()
8382 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in elink_8073_config_init()
8385 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in elink_8073_config_init()
8386 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in elink_8073_config_init()
8391 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in elink_8073_config_init()
8403 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in elink_8073_config_init()
8405 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in elink_8073_config_init()
8411 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8073_config_init()
8466 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); in elink_8073_read_status()
8468 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); in elink_8073_read_status()
8548 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_8073_read_status()
9765 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); in elink_8706_8726_read_status()
9767 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); in elink_8706_8726_read_status()
9861 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); in elink_8706_config_init()
9865 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); in elink_8706_config_init()
9868 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in elink_8706_config_init()
9871 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); in elink_8706_config_init()
9875 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8706_config_init()
10023 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); in elink_8726_config_init()
10025 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); in elink_8726_config_init()
10027 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); in elink_8726_config_init()
10029 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in elink_8726_config_init()
10031 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in elink_8726_config_init()
10181 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); in elink_8727_config_speed()
10183 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); in elink_8727_config_speed()
10189 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, in elink_8727_config_speed()
10192 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); in elink_8727_config_speed()
10635 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} in elink_848xx_set_led()
10699 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, in elink_848xx_cmn_config_init()
10704 MDIO_AN_DEVAD, in elink_848xx_cmn_config_init()
10708 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, in elink_848xx_cmn_config_init()
10727 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, in elink_848xx_cmn_config_init()
10775 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, in elink_848xx_cmn_config_init()
10787 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, in elink_848xx_cmn_config_init()
10793 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, in elink_848xx_cmn_config_init()
10805 MDIO_AN_DEVAD, in elink_848xx_cmn_config_init()
10817 MDIO_AN_DEVAD, in elink_848xx_cmn_config_init()
10821 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, in elink_848xx_cmn_config_init()
10825 MDIO_AN_DEVAD, in elink_848xx_cmn_config_init()
11108 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_84833_hw_reset_phy()
11111 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_84833_hw_reset_phy()
11217 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_848x3_config_init()
11356 MDIO_AN_DEVAD, 0xFFFA, &val1); in elink_848xx_read_status()
11373 MDIO_AN_DEVAD, in elink_848xx_read_status()
11378 MDIO_AN_DEVAD, in elink_848xx_read_status()
11402 MDIO_AN_DEVAD, in elink_848xx_read_status()
11421 MDIO_AN_DEVAD, in elink_848xx_read_status()
11428 MDIO_AN_DEVAD, in elink_848xx_read_status()
11442 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_848xx_read_status()
11460 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_848xx_read_status()
11470 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_848xx_read_status()
11507 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in elink_8481_link_reset()
12031 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, in elink_54618se_config_init()
12294 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); in elink_7101_config_init()
12297 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); in elink_7101_config_init()
12333 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, in elink_7101_read_status()
14921 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_check_kr2_wa()
14923 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, in elink_check_kr2_wa()