Lines Matching refs:OP_IF_MODE_AND
62 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
64 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
66 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
68 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
70 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
72 {OP_IF_MODE_AND, 4, 0x2020}, /* e3_b0+port2 */
77 {OP_IF_MODE_AND, 3, 0x2040}, /* e3_b0+port4 */
84 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
86 {OP_IF_MODE_AND, 2, 0x2020}, /* e3_b0+port2 */
89 {OP_IF_MODE_AND, 2, 0x2040}, /* e3_b0+port4 */
94 {OP_IF_MODE_AND, 2, 0x2040}, /* e3_b0+port4 */
114 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
154 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
211 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
213 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
215 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
217 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
219 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
221 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
223 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
225 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
227 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
516 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
519 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
522 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
525 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
528 {OP_IF_MODE_AND, 2, 0x1000}, /* e3_a0 */
531 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
534 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
537 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
540 {OP_IF_MODE_AND, 2, 0x2000}, /* e3_b0 */
543 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
546 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
549 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
554 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
556 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
558 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
560 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
562 {OP_IF_MODE_AND, 4, 0x10}, /* e3 */
567 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
582 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
659 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
661 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
698 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
743 {OP_IF_MODE_AND, 1, 0x88}, /* e2+sf */
745 {OP_IF_MODE_AND, 1, 0x108}, /* e2+mf */
749 {OP_IF_MODE_AND, 1, 0x90}, /* e3+sf */
751 {OP_IF_MODE_AND, 1, 0x110}, /* e3+mf */
755 {OP_IF_MODE_AND, 1, 0x90}, /* e3+sf */
757 {OP_IF_MODE_AND, 1, 0x110}, /* e3+mf */
786 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
813 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
816 {OP_IF_MODE_AND, 1, 0x80}, /* sf */
818 {OP_IF_MODE_AND, 1, 0x200}, /* mf_sd */
820 {OP_IF_MODE_AND, 1, 0x400}, /* mf_si */
822 {OP_IF_MODE_AND, 1, 0x800}, /* mf_afex */
824 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
852 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
855 {OP_IF_MODE_AND, 1, 0x80}, /* sf */
857 {OP_IF_MODE_AND, 1, 0x200}, /* mf_sd */
859 {OP_IF_MODE_AND, 1, 0x400}, /* mf_si */
861 {OP_IF_MODE_AND, 1, 0x800}, /* mf_afex */
863 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
899 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
905 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
912 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
919 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
980 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
1056 {OP_IF_MODE_AND, 20, 0x8}, /* e2 */
1077 {OP_IF_MODE_AND, 28, 0x1000}, /* e3_a0 */
1106 {OP_IF_MODE_AND, 14, 0x1020}, /* e3_a0+port2 */
1121 {OP_IF_MODE_AND, 14, 0x1040}, /* e3_a0+port4 */
1136 {OP_IF_MODE_AND, 7, 0x2000}, /* e3_b0 */
1144 {OP_IF_MODE_AND, 15, 0x4020}, /* cos3+port2 */
1160 {OP_IF_MODE_AND, 13, 0x4040}, /* cos3+port4 */
1174 {OP_IF_MODE_AND, 13, 0x8000}, /* cos6 */
1208 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1211 {OP_IF_MODE_AND, 2, 0x10}, /* e3 */
1252 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1254 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1256 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1258 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1260 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1262 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1264 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1266 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1268 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1307 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1309 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1311 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1313 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1315 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1317 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1319 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1321 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1323 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1345 {OP_IF_MODE_AND, 3, 0x8}, /* e2 */
1349 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1352 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1355 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1358 {OP_IF_MODE_AND, 1, 0x20}, /* port2 */
1360 {OP_IF_MODE_AND, 1, 0x40}, /* port4 */
1362 {OP_IF_MODE_AND, 3, 0x1000}, /* e3_a0 */
1366 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1369 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1372 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1375 {OP_IF_MODE_AND, 3, 0x2000}, /* e3_b0 */
1379 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1382 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1385 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1388 {OP_IF_MODE_AND, 1, 0x4000}, /* cos3 */
1390 {OP_IF_MODE_AND, 1, 0x8000}, /* cos6 */
1395 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1397 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1399 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1401 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1404 {OP_IF_MODE_AND, 7, 0x10}, /* e3 */
1413 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1428 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
1531 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
1588 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1590 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1592 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1594 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1596 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1598 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1600 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1602 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1604 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1622 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1625 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1628 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1631 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1634 {OP_IF_MODE_AND, 2, 0x1000}, /* e3_a0 */
1637 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1640 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1643 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1646 {OP_IF_MODE_AND, 2, 0x2000}, /* e3_b0 */
1649 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1652 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1655 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1660 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1662 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1664 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1666 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
1668 {OP_IF_MODE_AND, 4, 0x10}, /* e3 */
1673 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1688 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
1905 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1907 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1909 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1911 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1913 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1915 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1917 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1919 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1921 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1942 {OP_IF_MODE_AND, 3, 0x8}, /* e2 */
1946 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1949 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1952 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1955 {OP_IF_MODE_AND, 3, 0x20}, /* port2 */
1959 {OP_IF_MODE_AND, 2, 0x40}, /* port4 */
1962 {OP_IF_MODE_AND, 3, 0x1000}, /* e3_a0 */
1966 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1969 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1972 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1975 {OP_IF_MODE_AND, 3, 0x2000}, /* e3_b0 */
1979 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1982 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1985 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1988 {OP_IF_MODE_AND, 1, 0x4000}, /* cos3 */
1990 {OP_IF_MODE_AND, 1, 0x8000}, /* cos6 */
1995 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1997 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1999 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
2001 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
2004 {OP_IF_MODE_AND, 7, 0x10}, /* e3 */
2013 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
2028 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */