Lines Matching refs:pdata
122 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) in xgbe_get_max_frame() argument
124 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in xgbe_get_max_frame()
128 xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec) in xgbe_usec_to_riwt() argument
133 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
147 xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt) in xgbe_riwt_to_usec() argument
152 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
166 xgbe_config_pbl_val(struct xgbe_prv_data *pdata) in xgbe_config_pbl_val() argument
172 pbl = pdata->pbl; in xgbe_config_pbl_val()
174 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
179 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
180 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
183 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
184 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
187 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
188 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
196 xgbe_config_osp_mode(struct xgbe_prv_data *pdata) in xgbe_config_osp_mode() argument
200 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
201 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
204 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
205 pdata->tx_osp_mode); in xgbe_config_osp_mode()
212 xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rsf_mode() argument
216 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
217 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
223 xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tsf_mode() argument
227 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
228 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
234 xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rx_threshold() argument
238 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
239 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
245 xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tx_threshold() argument
249 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
250 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
256 xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_rx_coalesce() argument
260 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
261 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
264 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
265 pdata->rx_riwt); in xgbe_config_rx_coalesce()
272 xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_tx_coalesce() argument
278 xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_buffer_size() argument
282 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
283 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
286 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
287 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
292 xgbe_config_tso_mode(struct xgbe_prv_data *pdata) in xgbe_config_tso_mode() argument
296 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO); in xgbe_config_tso_mode()
298 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
299 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
303 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0); in xgbe_config_tso_mode()
308 xgbe_config_sph_mode(struct xgbe_prv_data *pdata) in xgbe_config_sph_mode() argument
311 int sph_enable_flag = XGMAC_IOREAD_BITS(pdata, MAC_HWF1R, SPHEN); in xgbe_config_sph_mode()
314 pdata->sph_enable, sph_enable_flag); in xgbe_config_sph_mode()
316 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
319 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
320 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
322 if (pdata->sph_enable && sph_enable_flag) { in xgbe_config_sph_mode()
324 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
327 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); in xgbe_config_sph_mode()
331 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH); in xgbe_config_sph_mode()
336 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
337 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); in xgbe_config_sph_mode()
341 xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, in xgbe_write_rss_reg() argument
347 mtx_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
349 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { in xgbe_write_rss_reg()
354 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); in xgbe_write_rss_reg()
356 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in xgbe_write_rss_reg()
357 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in xgbe_write_rss_reg()
358 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in xgbe_write_rss_reg()
359 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in xgbe_write_rss_reg()
363 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in xgbe_write_rss_reg()
372 mtx_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
378 xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) in xgbe_write_rss_hash_key() argument
380 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t); in xgbe_write_rss_hash_key()
381 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
385 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, in xgbe_write_rss_hash_key()
395 xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) in xgbe_write_rss_lookup_table() argument
400 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
401 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i, in xgbe_write_rss_lookup_table()
402 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
411 xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key) in xgbe_set_rss_hash_key() argument
413 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
415 return (xgbe_write_rss_hash_key(pdata)); in xgbe_set_rss_hash_key()
419 xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table) in xgbe_set_rss_lookup_table() argument
423 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
424 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
426 return (xgbe_write_rss_lookup_table(pdata)); in xgbe_set_rss_lookup_table()
430 xgbe_enable_rss(struct xgbe_prv_data *pdata) in xgbe_enable_rss() argument
434 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
438 ret = xgbe_write_rss_hash_key(pdata); in xgbe_enable_rss()
443 ret = xgbe_write_rss_lookup_table(pdata); in xgbe_enable_rss()
448 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
451 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in xgbe_enable_rss()
459 xgbe_disable_rss(struct xgbe_prv_data *pdata) in xgbe_disable_rss() argument
461 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
464 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in xgbe_disable_rss()
472 xgbe_config_rss(struct xgbe_prv_data *pdata) in xgbe_config_rss() argument
476 if (!pdata->hw_feat.rss) in xgbe_config_rss()
480 if (pdata->enable_rss) in xgbe_config_rss()
481 ret = xgbe_enable_rss(pdata); in xgbe_config_rss()
483 ret = xgbe_disable_rss(pdata); in xgbe_config_rss()
490 xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_tx_flow_control() argument
497 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
498 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
502 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_disable_tx_flow_control()
505 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
507 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
516 xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_tx_flow_control() argument
523 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
526 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
532 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
540 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_enable_tx_flow_control()
543 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
551 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
560 xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_rx_flow_control() argument
562 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in xgbe_disable_rx_flow_control()
568 xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_rx_flow_control() argument
570 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in xgbe_enable_rx_flow_control()
576 xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_tx_flow_control() argument
578 if (pdata->tx_pause) in xgbe_config_tx_flow_control()
579 xgbe_enable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
581 xgbe_disable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
587 xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_rx_flow_control() argument
589 if (pdata->rx_pause) in xgbe_config_rx_flow_control()
590 xgbe_enable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
592 xgbe_disable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
598 xgbe_config_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_flow_control() argument
600 xgbe_config_tx_flow_control(pdata); in xgbe_config_flow_control()
601 xgbe_config_rx_flow_control(pdata); in xgbe_config_flow_control()
603 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); in xgbe_config_flow_control()
607 xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_dma_interrupts() argument
613 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
614 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, in xgbe_enable_dma_interrupts()
615 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
617 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
619 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
620 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
649 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
661 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
671 xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mtl_interrupts() argument
676 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
679 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in xgbe_enable_mtl_interrupts()
680 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in xgbe_enable_mtl_interrupts()
683 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in xgbe_enable_mtl_interrupts()
688 xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mac_interrupts() argument
695 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); in xgbe_enable_mac_interrupts()
698 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
699 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
702 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); in xgbe_enable_mac_interrupts()
706 xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_set_speed() argument
724 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in xgbe_set_speed()
725 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in xgbe_set_speed()
731 xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_stripping() argument
734 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); in xgbe_enable_rx_vlan_stripping()
737 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); in xgbe_enable_rx_vlan_stripping()
740 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); in xgbe_enable_rx_vlan_stripping()
743 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); in xgbe_enable_rx_vlan_stripping()
746 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); in xgbe_enable_rx_vlan_stripping()
754 xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_stripping() argument
756 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); in xgbe_disable_rx_vlan_stripping()
764 xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_filtering() argument
767 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); in xgbe_enable_rx_vlan_filtering()
770 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); in xgbe_enable_rx_vlan_filtering()
773 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); in xgbe_enable_rx_vlan_filtering()
776 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); in xgbe_enable_rx_vlan_filtering()
784 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); in xgbe_enable_rx_vlan_filtering()
792 xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_filtering() argument
795 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); in xgbe_disable_rx_vlan_filtering()
828 xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) in xgbe_update_vlan_hash_table() argument
836 XGMAC_IOREAD(pdata, MAC_VLANHTR)); in xgbe_update_vlan_hash_table()
839 for_each_set_bit(vid, pdata->active_vlans, VLAN_NVID) { in xgbe_update_vlan_hash_table()
852 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); in xgbe_update_vlan_hash_table()
855 XGMAC_IOREAD(pdata, MAC_VLANHTR)); in xgbe_update_vlan_hash_table()
861 xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable) in xgbe_set_promiscuous_mode() argument
865 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) in xgbe_set_promiscuous_mode()
870 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); in xgbe_set_promiscuous_mode()
875 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
877 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_set_promiscuous_mode()
879 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
887 xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable) in xgbe_set_all_multicast_mode() argument
891 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) in xgbe_set_all_multicast_mode()
895 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); in xgbe_set_all_multicast_mode()
901 xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg) in xgbe_set_mac_reg() argument
924 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); in xgbe_set_mac_reg()
926 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); in xgbe_set_mac_reg()
931 xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) in xgbe_set_mac_addn_addrs() argument
937 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
939 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); in xgbe_set_mac_addn_addrs()
944 xgbe_set_mac_reg(pdata, NULL, &mac_reg); in xgbe_set_mac_addn_addrs()
948 xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) in xgbe_add_mac_addresses() argument
951 xgbe_set_mac_addn_addrs(pdata); in xgbe_add_mac_addresses()
957 xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr) in xgbe_set_mac_address() argument
965 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in xgbe_set_mac_address()
966 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in xgbe_set_mac_address()
972 xgbe_config_rx_mode(struct xgbe_prv_data *pdata) in xgbe_config_rx_mode() argument
976 pr_mode = ((pdata->netdev->if_flags & IFF_PPROMISC) != 0); in xgbe_config_rx_mode()
977 am_mode = ((pdata->netdev->if_flags & IFF_ALLMULTI) != 0); in xgbe_config_rx_mode()
979 xgbe_set_promiscuous_mode(pdata, pr_mode); in xgbe_config_rx_mode()
980 xgbe_set_all_multicast_mode(pdata, am_mode); in xgbe_config_rx_mode()
982 xgbe_add_mac_addresses(pdata); in xgbe_config_rx_mode()
988 xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_clr_gpio() argument
995 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_clr_gpio()
998 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_clr_gpio()
1004 xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_set_gpio() argument
1011 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_set_gpio()
1014 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_set_gpio()
1020 xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs_v2() argument
1029 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1041 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1042 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1044 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1045 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1046 mmd_data = XPCS16_IOREAD(pdata, offset); in xgbe_read_mmd_regs_v2()
1047 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1053 xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs_v2() argument
1062 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1074 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1075 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1077 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1078 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1079 XPCS16_IOWRITE(pdata, offset, mmd_data); in xgbe_write_mmd_regs_v2()
1080 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1084 xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs_v1() argument
1093 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1104 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1105 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_read_mmd_regs_v1()
1106 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); in xgbe_read_mmd_regs_v1()
1107 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1113 xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs_v1() argument
1122 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1133 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1134 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_write_mmd_regs_v1()
1135 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); in xgbe_write_mmd_regs_v1()
1136 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1140 xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) in xgbe_read_mmd_regs() argument
1142 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1144 return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg)); in xgbe_read_mmd_regs()
1148 return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg)); in xgbe_read_mmd_regs()
1153 xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, in xgbe_write_mmd_regs() argument
1156 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1158 return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data)); in xgbe_write_mmd_regs()
1162 return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data)); in xgbe_write_mmd_regs()
1182 xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg, in xgbe_write_ext_mii_regs() argument
1187 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1190 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_write_ext_mii_regs()
1196 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_write_ext_mii_regs()
1198 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_write_ext_mii_regs()
1201 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1205 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1210 xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg) in xgbe_read_ext_mii_regs() argument
1214 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1217 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_read_ext_mii_regs()
1222 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_read_ext_mii_regs()
1224 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_read_ext_mii_regs()
1227 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1231 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1233 return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA)); in xgbe_read_ext_mii_regs()
1237 xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, in xgbe_set_ext_mii_mode() argument
1240 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode()
1254 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in xgbe_set_ext_mii_mode()
1266 xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_disable_rx_csum() argument
1268 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in xgbe_disable_rx_csum()
1275 xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_enable_rx_csum() argument
1277 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in xgbe_enable_rx_csum()
1355 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read() local
1397 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1474 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
1482 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
1523 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_enable_int() local
1572 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_disable_int() local
1620 __xgbe_exit(struct xgbe_prv_data *pdata) in __xgbe_exit() argument
1625 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __xgbe_exit()
1629 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
1639 xgbe_exit(struct xgbe_prv_data *pdata) in xgbe_exit() argument
1646 ret = __xgbe_exit(pdata); in xgbe_exit()
1652 return (__xgbe_exit(pdata)); in xgbe_exit()
1656 xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) in xgbe_flush_tx_queues() argument
1660 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
1663 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
1664 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
1667 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
1669 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
1681 xgbe_config_dma_bus(struct xgbe_prv_data *pdata) in xgbe_config_dma_bus() argument
1685 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); in xgbe_config_dma_bus()
1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
1694 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
1695 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
1697 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); in xgbe_config_dma_bus()
1700 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
1701 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, in xgbe_config_dma_bus()
1702 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
1704 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
1705 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, in xgbe_config_dma_bus()
1706 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
1710 xgbe_config_dma_cache(struct xgbe_prv_data *pdata) in xgbe_config_dma_cache() argument
1712 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
1713 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
1714 if (pdata->awarcr) in xgbe_config_dma_cache()
1715 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
1719 xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) in xgbe_config_mtl_mode() argument
1724 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in xgbe_config_mtl_mode()
1727 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
1728 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_mtl_mode()
1730 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in xgbe_config_mtl_mode()
1734 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in xgbe_config_mtl_mode()
1738 xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_queue_flow_control_threshold() argument
1744 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_queue_flow_control_threshold()
1757 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
1758 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
1764 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
1765 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
1771 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
1772 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
1792 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
1793 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
1795 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]); in xgbe_queue_flow_control_threshold()
1799 xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_calculate_flow_control_threshold() argument
1805 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
1810 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in xgbe_calculate_flow_control_threshold()
1815 xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) in xgbe_config_flow_control_threshold() argument
1819 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
1821 pdata->rx_rfa[i], pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1823 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in xgbe_config_flow_control_threshold()
1824 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
1825 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in xgbe_config_flow_control_threshold()
1826 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1829 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); in xgbe_config_flow_control_threshold()
1834 xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_tx_fifo_size() argument
1837 return (min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
1838 pdata->hw_feat.tx_fifo_size)); in xgbe_get_tx_fifo_size()
1842 xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_rx_fifo_size() argument
1845 return (min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
1846 pdata->hw_feat.rx_fifo_size)); in xgbe_get_rx_fifo_size()
1896 xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_tx_fifo_size() argument
1902 fifo_size = xgbe_get_tx_fifo_size(pdata); in xgbe_config_tx_fifo_size()
1905 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
1907 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_config_tx_fifo_size()
1908 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
1910 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); in xgbe_config_tx_fifo_size()
1914 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
1918 xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_fifo_size() argument
1928 fifo_size = xgbe_get_rx_fifo_size(pdata); in xgbe_config_rx_fifo_size()
1929 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
1931 fifo_size, pdata->rx_q_count, prio_queues); in xgbe_config_rx_fifo_size()
1934 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
1938 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_rx_fifo_size()
1939 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
1941 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); in xgbe_config_rx_fifo_size()
1944 xgbe_calculate_flow_control_threshold(pdata, fifo); in xgbe_config_rx_fifo_size()
1945 xgbe_config_flow_control_threshold(pdata); in xgbe_config_rx_fifo_size()
1948 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_rx_fifo_size()
1952 xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) in xgbe_config_queue_mapping() argument
1963 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1964 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1966 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
1969 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
1971 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1976 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
1978 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1983 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
1994 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2000 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2008 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2016 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2019 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2022 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2030 xgbe_config_mac_address(struct xgbe_prv_data *pdata) in xgbe_config_mac_address() argument
2032 xgbe_set_mac_address(pdata, IF_LLADDR(pdata->netdev)); in xgbe_config_mac_address()
2035 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2036 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); in xgbe_config_mac_address()
2037 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); in xgbe_config_mac_address()
2038 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); in xgbe_config_mac_address()
2043 xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) in xgbe_config_jumbo_enable() argument
2047 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2049 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in xgbe_config_jumbo_enable()
2053 xgbe_config_mac_speed(struct xgbe_prv_data *pdata) in xgbe_config_mac_speed() argument
2055 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2059 xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) in xgbe_config_checksum_offload() argument
2061 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM)) in xgbe_config_checksum_offload()
2062 xgbe_enable_rx_csum(pdata); in xgbe_config_checksum_offload()
2064 xgbe_disable_rx_csum(pdata); in xgbe_config_checksum_offload()
2068 xgbe_config_vlan_support(struct xgbe_prv_data *pdata) in xgbe_config_vlan_support() argument
2071 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); in xgbe_config_vlan_support()
2072 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); in xgbe_config_vlan_support()
2075 xgbe_update_vlan_hash_table(pdata); in xgbe_config_vlan_support()
2077 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_config_vlan_support()
2079 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2082 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2085 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { in xgbe_config_vlan_support()
2087 xgbe_enable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2090 xgbe_disable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2095 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) in xgbe_mmc_read() argument
2100 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2129 val = XGMAC_IOREAD(pdata, reg_lo); in xgbe_mmc_read()
2132 val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); in xgbe_mmc_read()
2138 xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_tx_mmc_int() argument
2140 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2141 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); in xgbe_tx_mmc_int()
2145 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_tx_mmc_int()
2149 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_tx_mmc_int()
2153 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2157 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2161 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_tx_mmc_int()
2165 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_tx_mmc_int()
2169 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_tx_mmc_int()
2173 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_tx_mmc_int()
2177 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_tx_mmc_int()
2181 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_tx_mmc_int()
2185 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2189 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2193 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2197 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_tx_mmc_int()
2201 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_tx_mmc_int()
2205 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_tx_mmc_int()
2209 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_tx_mmc_int()
2213 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_tx_mmc_int()
2217 xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_rx_mmc_int() argument
2219 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2220 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); in xgbe_rx_mmc_int()
2224 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_rx_mmc_int()
2228 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_rx_mmc_int()
2232 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_rx_mmc_int()
2236 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2240 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2244 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_rx_mmc_int()
2248 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_rx_mmc_int()
2252 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_rx_mmc_int()
2256 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_rx_mmc_int()
2260 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_rx_mmc_int()
2264 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_rx_mmc_int()
2268 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_rx_mmc_int()
2272 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_rx_mmc_int()
2276 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_rx_mmc_int()
2280 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_rx_mmc_int()
2284 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_rx_mmc_int()
2288 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2292 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_rx_mmc_int()
2296 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_rx_mmc_int()
2300 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_rx_mmc_int()
2304 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_rx_mmc_int()
2308 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_rx_mmc_int()
2312 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_rx_mmc_int()
2316 xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) in xgbe_read_mmc_stats() argument
2318 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
2321 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); in xgbe_read_mmc_stats()
2324 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
2327 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
2330 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2333 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2336 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
2339 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
2342 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
2345 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
2348 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
2351 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
2354 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2357 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2360 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
2363 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_read_mmc_stats()
2366 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
2369 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_read_mmc_stats()
2372 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
2375 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_read_mmc_stats()
2378 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
2381 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
2384 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
2387 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2390 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2393 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_read_mmc_stats()
2396 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_read_mmc_stats()
2399 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_read_mmc_stats()
2402 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_read_mmc_stats()
2405 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_read_mmc_stats()
2408 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
2411 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
2414 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
2417 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
2420 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
2423 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
2426 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
2429 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_read_mmc_stats()
2432 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_read_mmc_stats()
2435 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
2438 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_read_mmc_stats()
2441 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_read_mmc_stats()
2444 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_read_mmc_stats()
2447 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); in xgbe_read_mmc_stats()
2451 xgbe_config_mmc(struct xgbe_prv_data *pdata) in xgbe_config_mmc() argument
2454 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
2457 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in xgbe_config_mmc()
2461 xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_txq_prepare_tx_stop() argument
2472 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); in xgbe_txq_prepare_tx_stop()
2486 xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_prepare_tx_stop() argument
2492 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
2493 return (xgbe_txq_prepare_tx_stop(pdata, queue)); in xgbe_prepare_tx_stop()
2513 tx_status = XGMAC_IOREAD(pdata, tx_dsr); in xgbe_prepare_tx_stop()
2528 xgbe_enable_tx(struct xgbe_prv_data *pdata) in xgbe_enable_tx() argument
2533 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
2534 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
2537 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
2541 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
2542 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
2546 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_enable_tx()
2550 xgbe_disable_tx(struct xgbe_prv_data *pdata) in xgbe_disable_tx() argument
2555 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2556 xgbe_prepare_tx_stop(pdata, i); in xgbe_disable_tx()
2559 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_disable_tx()
2562 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2563 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
2566 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
2567 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
2570 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
2575 xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue) in xgbe_prepare_rx_stop() argument
2586 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); in xgbe_prepare_rx_stop()
2600 xgbe_enable_rx(struct xgbe_prv_data *pdata) in xgbe_enable_rx() argument
2605 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
2606 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
2609 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
2614 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
2616 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); in xgbe_enable_rx()
2619 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); in xgbe_enable_rx()
2620 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); in xgbe_enable_rx()
2621 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); in xgbe_enable_rx()
2622 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); in xgbe_enable_rx()
2626 xgbe_disable_rx(struct xgbe_prv_data *pdata) in xgbe_disable_rx() argument
2631 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); in xgbe_disable_rx()
2632 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); in xgbe_disable_rx()
2633 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); in xgbe_disable_rx()
2634 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); in xgbe_disable_rx()
2637 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
2638 xgbe_prepare_rx_stop(pdata, i); in xgbe_disable_rx()
2641 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); in xgbe_disable_rx()
2644 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
2645 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
2648 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
2653 xgbe_powerup_tx(struct xgbe_prv_data *pdata) in xgbe_powerup_tx() argument
2658 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
2659 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
2662 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
2666 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_powerup_tx()
2670 xgbe_powerdown_tx(struct xgbe_prv_data *pdata) in xgbe_powerdown_tx() argument
2675 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
2676 xgbe_prepare_tx_stop(pdata, i); in xgbe_powerdown_tx()
2679 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_powerdown_tx()
2682 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
2683 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
2686 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
2691 xgbe_powerup_rx(struct xgbe_prv_data *pdata) in xgbe_powerup_rx() argument
2696 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
2697 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
2700 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
2705 xgbe_powerdown_rx(struct xgbe_prv_data *pdata) in xgbe_powerdown_rx() argument
2710 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
2711 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
2714 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
2719 xgbe_init(struct xgbe_prv_data *pdata) in xgbe_init() argument
2721 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
2725 ret = xgbe_flush_tx_queues(pdata); in xgbe_init()
2734 xgbe_config_dma_bus(pdata); in xgbe_init()
2735 xgbe_config_dma_cache(pdata); in xgbe_init()
2736 xgbe_config_osp_mode(pdata); in xgbe_init()
2737 xgbe_config_pbl_val(pdata); in xgbe_init()
2738 xgbe_config_rx_coalesce(pdata); in xgbe_init()
2739 xgbe_config_tx_coalesce(pdata); in xgbe_init()
2740 xgbe_config_rx_buffer_size(pdata); in xgbe_init()
2741 xgbe_config_tso_mode(pdata); in xgbe_init()
2742 xgbe_config_sph_mode(pdata); in xgbe_init()
2743 xgbe_config_rss(pdata); in xgbe_init()
2744 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
2745 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
2746 xgbe_enable_dma_interrupts(pdata); in xgbe_init()
2751 xgbe_config_mtl_mode(pdata); in xgbe_init()
2752 xgbe_config_queue_mapping(pdata); in xgbe_init()
2753 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
2754 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
2755 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
2756 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
2757 xgbe_config_tx_fifo_size(pdata); in xgbe_init()
2758 xgbe_config_rx_fifo_size(pdata); in xgbe_init()
2762 xgbe_enable_mtl_interrupts(pdata); in xgbe_init()
2767 xgbe_config_mac_address(pdata); in xgbe_init()
2768 xgbe_config_rx_mode(pdata); in xgbe_init()
2769 xgbe_config_jumbo_enable(pdata); in xgbe_init()
2770 xgbe_config_flow_control(pdata); in xgbe_init()
2771 xgbe_config_mac_speed(pdata); in xgbe_init()
2772 xgbe_config_checksum_offload(pdata); in xgbe_init()
2773 xgbe_config_vlan_support(pdata); in xgbe_init()
2774 xgbe_config_mmc(pdata); in xgbe_init()
2775 xgbe_enable_mac_interrupts(pdata); in xgbe_init()