Lines Matching refs:ProcModel
95 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
97 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
99 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
103 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
105 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
108 const CodeGenProcModel &ProcModel);
110 const CodeGenProcModel &ProcModel);
112 const CodeGenProcModel &ProcModel);
113 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
385 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
387 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second) in EmitStageAndOperandCycleData()
390 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
394 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
404 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
438 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
445 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
448 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
451 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
457 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
621 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
622 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
626 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResourceSubUnits()
627 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResourceSubUnits()
633 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc()); in EmitProcessorResourceSubUnits()
635 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
643 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, in EmitRetireControlUnitInfo() argument
646 if (Record *RCU = ProcModel.RetireControlUnit) { in EmitRetireControlUnitInfo()
657 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, in EmitRegisterFileInfo() argument
661 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
667 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
674 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, in EmitRegisterFileTables() argument
676 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { in EmitRegisterFileTables()
683 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
687 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
706 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
712 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
726 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, in EmitLoadStoreQueueInfo() argument
729 if (ProcModel.LoadQueue) { in EmitLoadStoreQueueInfo()
730 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
731 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
732 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
737 if (ProcModel.StoreQueue) { in EmitLoadStoreQueueInfo()
739 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
740 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
741 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
746 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, in EmitExtraProcessorInfo() argument
750 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
753 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
757 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
761 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), in EmitExtraProcessorInfo()
765 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
770 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources() argument
772 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
775 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
781 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResources()
782 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResources()
801 ProcModel, PRDef->getLoc()); in EmitProcessorResources()
802 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); in EmitProcessorResources()
812 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
828 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
841 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
846 "defined for processor " + ProcModel.ModelName + in FindWriteResources()
855 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
863 ProcModel.ModelName); in FindWriteResources()
871 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
881 const CodeGenProcModel &ProcModel) { in FindReadAdvance() argument
893 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
898 "defined for processor " + ProcModel.ModelName + in FindReadAdvance()
907 for (Record *RA : ProcModel.ReadAdvanceDefs) { in FindReadAdvance()
915 ProcModel.ModelName); in FindReadAdvance()
923 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
979 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables() argument
982 if (!ProcModel.hasInstrSchedModel()) in GenSchedClassTables()
1005 if (CGT.ProcIndex == ProcModel.Index) { in GenSchedClassTables()
1020 if (!is_contained(SC.ProcIndices, ProcModel.Index)) in GenSchedClassTables()
1031 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { in GenSchedClassTables()
1045 for (Record *I : ProcModel.ItinRWDefs) { in GenSchedClassTables()
1054 LLVM_DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
1068 ProcModel); in GenSchedClassTables()
1086 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); in GenSchedClassTables()
1121 ExpandProcResources(PRVec, Cycles, ProcModel); in GenSchedClassTables()
1126 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); in GenSchedClassTables()
1152 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1413 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel() local
1414 GenSchedClassTables(ProcModel, SchedTables); in EmitSchedModel()