Lines Matching refs:OS
76 void Enumeration(raw_ostream &OS, DenseMap<Record *, unsigned> &FeatureMap);
77 unsigned FeatureKeyValues(raw_ostream &OS,
79 unsigned CPUKeyValues(raw_ostream &OS,
89 void EmitStageAndOperandCycleData(raw_ostream &OS,
92 void EmitItineraries(raw_ostream &OS,
96 raw_ostream &OS);
98 raw_ostream &OS);
100 raw_ostream &OS);
101 void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
104 raw_ostream &OS);
106 raw_ostream &OS);
115 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
116 void EmitProcessorModels(raw_ostream &OS);
117 void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
118 void emitSchedModelHelpersImpl(raw_ostream &OS,
120 void emitGenMCSubtargetInfo(raw_ostream &OS);
121 void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
123 void EmitSchedModel(raw_ostream &OS);
124 void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
125 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
141 void SubtargetEmitter::Enumeration(raw_ostream &OS, in Enumeration() argument
154 OS << "namespace " << Target << " {\n"; in Enumeration()
157 OS << "enum {\n"; in Enumeration()
165 OS << " " << Def->getName() << " = " << i << ",\n"; in Enumeration()
171 OS << " " in Enumeration()
175 OS << "};\n"; in Enumeration()
176 OS << "} // end namespace " << Target << "\n"; in Enumeration()
179 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask() argument
187 OS << "{ { { "; in printFeatureMask()
189 OS << "0x"; in printFeatureMask()
190 OS.write_hex(Mask[i]); in printFeatureMask()
191 OS << "ULL, "; in printFeatureMask()
193 OS << "} } }"; in printFeatureMask()
201 raw_ostream &OS, const DenseMap<Record *, unsigned> &FeatureMap) { in FeatureKeyValues() argument
212 OS << "// Sorted (by key) array of values for CPU features.\n" in FeatureKeyValues()
227 OS << " { " in FeatureKeyValues()
234 printFeatureMask(OS, ImpliesList, FeatureMap); in FeatureKeyValues()
236 OS << " },\n"; in FeatureKeyValues()
241 OS << "};\n"; in FeatureKeyValues()
251 SubtargetEmitter::CPUKeyValues(raw_ostream &OS, in CPUKeyValues() argument
259 OS << "// Sorted (by key) array of values for CPU subtype.\n" in CPUKeyValues()
270 OS << " { " in CPUKeyValues()
273 printFeatureMask(OS, FeatureList, FeatureMap); in CPUKeyValues()
274 OS << ", "; in CPUKeyValues()
275 printFeatureMask(OS, TuneFeatureList, FeatureMap); in CPUKeyValues()
280 OS << ", &" << ProcModelName << " },\n"; in CPUKeyValues()
284 OS << "};\n"; in CPUKeyValues()
378 EmitStageAndOperandCycleData(raw_ostream &OS, in EmitStageAndOperandCycleData() argument
395 OS << "\n// Functional units for \"" << Name << "\"\n" in EmitStageAndOperandCycleData()
399 OS << " const InstrStage::FuncUnits " << FUs[j]->getName() in EmitStageAndOperandCycleData()
402 OS << "} // end namespace " << Name << "FU\n"; in EmitStageAndOperandCycleData()
406 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name in EmitStageAndOperandCycleData()
409 OS << " const unsigned NoBypass = 0;\n"; in EmitStageAndOperandCycleData()
411 OS << " const unsigned " << BPs[j]->getName() in EmitStageAndOperandCycleData()
414 OS << "} // end namespace " << Name << "Bypass\n"; in EmitStageAndOperandCycleData()
543 OS << StageTable; in EmitStageAndOperandCycleData()
544 OS << OperandCycleTable; in EmitStageAndOperandCycleData()
545 OS << BypassTable; in EmitStageAndOperandCycleData()
555 EmitItineraries(raw_ostream &OS, in EmitItineraries() argument
579 OS << "\n"; in EmitItineraries()
580 OS << "static const llvm::InstrItinerary "; in EmitItineraries()
583 OS << ItinsDef->getName() << "[] = {\n"; in EmitItineraries()
591 OS << " { " << in EmitItineraries()
600 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }" in EmitItineraries()
602 OS << "};\n"; in EmitItineraries()
609 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, in EmitProcessorProp() argument
611 OS << " "; in EmitProcessorProp()
614 OS << V << Separator << " // " << Name; in EmitProcessorProp()
616 OS << "MCSchedModel::Default" << Name << Separator; in EmitProcessorProp()
617 OS << '\n'; in EmitProcessorProp()
621 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
622 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
635 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
638 OS << " // " << PRDef->getName() << "\n"; in EmitProcessorResourceSubUnits()
640 OS << "};\n"; in EmitProcessorResourceSubUnits()
644 raw_ostream &OS) { in EmitRetireControlUnitInfo() argument
653 OS << ReorderBufferSize << ", // ReorderBufferSize\n "; in EmitRetireControlUnitInfo()
654 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n "; in EmitRetireControlUnitInfo()
659 unsigned NumCostEntries, raw_ostream &OS) { in EmitRegisterFileInfo() argument
661 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
663 OS << "nullptr,\n 0"; in EmitRegisterFileInfo()
665 OS << ", // Number of register files.\n "; in EmitRegisterFileInfo()
667 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
669 OS << "nullptr,\n "; in EmitRegisterFileInfo()
670 OS << NumCostEntries << ", // Number of register cost entries.\n"; in EmitRegisterFileInfo()
675 raw_ostream &OS) { in EmitRegisterFileTables() argument
682 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n"; in EmitRegisterFileTables()
683 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
693 OS << " { "; in EmitRegisterFileTables()
696 OS << Rec->getValueAsString("Namespace") << "::"; in EmitRegisterFileTables()
697 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", " in EmitRegisterFileTables()
701 OS << "};\n"; in EmitRegisterFileTables()
704 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, " in EmitRegisterFileTables()
706 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
713 OS << " { "; in EmitRegisterFileTables()
714 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", "; in EmitRegisterFileTables()
716 OS << NumCostEntries << ", " << CostTblIndex << ", " in EmitRegisterFileTables()
721 OS << "};\n"; in EmitRegisterFileTables()
727 raw_ostream &OS) { in EmitLoadStoreQueueInfo() argument
734 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n"; in EmitLoadStoreQueueInfo()
743 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n"; in EmitLoadStoreQueueInfo()
747 raw_ostream &OS) { in EmitExtraProcessorInfo() argument
750 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
753 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
757 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
762 NumCostEntries, OS); in EmitExtraProcessorInfo()
765 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
767 OS << "};\n"; in EmitExtraProcessorInfo()
771 raw_ostream &OS) { in EmitProcessorResources() argument
772 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
774 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n"; in EmitProcessorResources()
775 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
807 OS << " {\"" << PRDef->getName() << "\", "; in EmitProcessorResources()
809 OS.indent(15 - PRDef->getName().size()); in EmitProcessorResources()
810 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", "; in EmitProcessorResources()
812 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
815 OS << "nullptr"; in EmitProcessorResources()
817 OS << "}, // #" << i+1; in EmitProcessorResources()
819 OS << ", Super=" << SuperDef->getName(); in EmitProcessorResources()
820 OS << "\n"; in EmitProcessorResources()
822 OS << "};\n"; in EmitProcessorResources()
1239 raw_ostream &OS) { in EmitSchedClassTables() argument
1241 OS << "\n// {ProcResourceIdx, Cycles}\n" in EmitSchedClassTables()
1248 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", " in EmitSchedClassTables()
1251 OS << ','; in EmitSchedClassTables()
1252 OS << " // #" << WPRIdx << '\n'; in EmitSchedClassTables()
1254 OS << "}; // " << Target << "WriteProcResTable\n"; in EmitSchedClassTables()
1257 OS << "\n// {Cycles, WriteResourceID}\n" in EmitSchedClassTables()
1264 OS << " {" << format("%2d", WLEntry.Cycles) << ", " in EmitSchedClassTables()
1267 OS << ','; in EmitSchedClassTables()
1268 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n'; in EmitSchedClassTables()
1270 OS << "}; // " << Target << "WriteLatencyTable\n"; in EmitSchedClassTables()
1273 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n" in EmitSchedClassTables()
1280 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
1284 OS << ','; in EmitSchedClassTables()
1285 OS << " // #" << RAIdx << '\n'; in EmitSchedClassTables()
1287 OS << "}; // " << Target << "ReadAdvanceTable\n"; in EmitSchedClassTables()
1298 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO," in EmitSchedClassTables()
1300 OS << "static const llvm::MCSchedClassDesc " in EmitSchedClassTables()
1307 OS << " {DBGFIELD(\"InvalidSchedClass\") " in EmitSchedClassTables()
1314 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1316 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()
1317 OS << MCDesc.NumMicroOps in EmitSchedClassTables()
1329 OS << "}; // " << PI->ModelName << "SchedClasses\n"; in EmitSchedClassTables()
1333 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { in EmitProcessorModels() argument
1338 EmitExtraProcessorInfo(PM, OS); in EmitProcessorModels()
1341 EmitProcessorResources(PM, OS); in EmitProcessorModels()
1347 OS << "\n"; in EmitProcessorModels()
1348 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n"; in EmitProcessorModels()
1349 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1350 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1351 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1352 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1353 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1354 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1359 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
1365 OS << " " << (CompleteModel ? "true" : "false") << ", // " in EmitProcessorModels()
1368 OS << " " << PM.Index << ", // Processor ID\n"; in EmitProcessorModels()
1370 OS << " " << PM.ModelName << "ProcResources" << ",\n" in EmitProcessorModels()
1376 OS << " nullptr, nullptr, 0, 0," in EmitProcessorModels()
1379 OS << " " << PM.ItinsDef->getName() << ",\n"; in EmitProcessorModels()
1381 OS << " nullptr, // No Itinerary\n"; in EmitProcessorModels()
1383 OS << " &" << PM.ModelName << "ExtraInfo,\n"; in EmitProcessorModels()
1385 OS << " nullptr // No extra processor descriptor\n"; in EmitProcessorModels()
1386 OS << "};\n"; in EmitProcessorModels()
1393 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { in EmitSchedModel() argument
1394 OS << "#ifdef DBGFIELD\n" in EmitSchedModel()
1406 EmitStageAndOperandCycleData(OS, ProcItinLists); in EmitSchedModel()
1407 EmitItineraries(OS, ProcItinLists); in EmitSchedModel()
1409 OS << "\n// ===============================================================\n" in EmitSchedModel()
1416 EmitSchedClassTables(SchedTables, OS); in EmitSchedModel()
1418 OS << "\n#undef DBGFIELD\n"; in EmitSchedModel()
1421 EmitProcessorModels(OS); in EmitSchedModel()
1424 static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) { in emitPredicateProlog() argument
1437 OS << Buffer; in emitPredicateProlog()
1447 raw_ostream &OS) { in emitPredicates() argument
1496 OS << Buffer; in emitPredicates()
1501 static void emitSchedModelHelperEpilogue(raw_ostream &OS, in emitSchedModelHelperEpilogue() argument
1504 OS << " // Don't know how to resolve this scheduling class.\n" in emitSchedModelHelperEpilogue()
1509 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"; in emitSchedModelHelperEpilogue()
1558 raw_ostream &OS, bool OnlyExpandMCInstPredicates) { in emitSchedModelHelpersImpl() argument
1564 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); in emitSchedModelHelpersImpl()
1575 OS << " switch (SchedClass) {\n"; in emitSchedModelHelpersImpl()
1581 OS << " case " << VC << ": // " << SC.Name << '\n'; in emitSchedModelHelpersImpl()
1587 OS << " "; in emitSchedModelHelpersImpl()
1591 OS << (OnlyExpandMCInstPredicates in emitSchedModelHelpersImpl()
1594 OS << PI << ") "; in emitSchedModelHelpersImpl()
1595 OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n'; in emitSchedModelHelpersImpl()
1620 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS); in emitSchedModelHelpersImpl()
1624 PE, OS); in emitSchedModelHelpersImpl()
1626 OS << " }\n"; in emitSchedModelHelpersImpl()
1633 OS << " return " << SC.Index << ";\n"; in emitSchedModelHelpersImpl()
1634 OS << " break;\n"; in emitSchedModelHelpersImpl()
1637 OS << " };\n"; in emitSchedModelHelpersImpl()
1639 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); in emitSchedModelHelpersImpl()
1643 raw_ostream &OS) { in EmitSchedModelHelpers() argument
1644 OS << "unsigned " << ClassName in EmitSchedModelHelpers()
1649 emitPredicateProlog(Records, OS); in EmitSchedModelHelpers()
1652 emitSchedModelHelpersImpl(OS); in EmitSchedModelHelpers()
1654 OS << "} // " << ClassName << "::resolveSchedClass\n\n"; in EmitSchedModelHelpers()
1656 OS << "unsigned " << ClassName in EmitSchedModelHelpers()
1670 PE.expandSTIPredicate(OS, Fn); in EmitSchedModelHelpers()
1674 raw_ostream &OS) { in EmitHwModeCheck() argument
1680 OS << "unsigned " << ClassName << "::getHwMode() const {\n"; in EmitHwModeCheck()
1683 OS << " if (checkFeatures(\"" << HM.Features in EmitHwModeCheck()
1686 OS << " return 0;\n}\n"; in EmitHwModeCheck()
1693 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, in ParseFeaturesFunction() argument
1700 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" in ParseFeaturesFunction()
1703 OS << Target; in ParseFeaturesFunction()
1704 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, " in ParseFeaturesFunction()
1711 OS << "}\n"; in ParseFeaturesFunction()
1715 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n" in ParseFeaturesFunction()
1725 OS << " if (Bits[" << Target << "::" in ParseFeaturesFunction()
1729 OS << " if (Bits[" << Target << "::" in ParseFeaturesFunction()
1735 OS << "}\n"; in ParseFeaturesFunction()
1738 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { in emitGenMCSubtargetInfo() argument
1739 OS << "namespace " << Target << "_MC {\n" in emitGenMCSubtargetInfo()
1742 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true); in emitGenMCSubtargetInfo()
1743 OS << "}\n"; in emitGenMCSubtargetInfo()
1744 OS << "} // end namespace " << Target << "_MC\n\n"; in emitGenMCSubtargetInfo()
1746 OS << "struct " << Target in emitGenMCSubtargetInfo()
1748 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n" in emitGenMCSubtargetInfo()
1763 OS << " }\n"; in emitGenMCSubtargetInfo()
1765 OS << " unsigned getHwMode() const override;\n"; in emitGenMCSubtargetInfo()
1766 OS << "};\n"; in emitGenMCSubtargetInfo()
1767 EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS); in emitGenMCSubtargetInfo()
1770 void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) { in EmitMCInstrAnalysisPredicateFunctions() argument
1771 OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n"; in EmitMCInstrAnalysisPredicateFunctions()
1772 OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1778 PE.expandSTIPredicate(OS, Fn); in EmitMCInstrAnalysisPredicateFunctions()
1780 OS << "#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1782 OS << "\n#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n"; in EmitMCInstrAnalysisPredicateFunctions()
1783 OS << "#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1790 PE.expandSTIPredicate(OS, Fn); in EmitMCInstrAnalysisPredicateFunctions()
1792 OS << "#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n"; in EmitMCInstrAnalysisPredicateFunctions()
1798 void SubtargetEmitter::run(raw_ostream &OS) { in run() argument
1799 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); in run()
1801 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; in run()
1802 OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; in run()
1806 OS << "namespace llvm {\n"; in run()
1807 Enumeration(OS, FeatureMap); in run()
1808 OS << "} // end namespace llvm\n\n"; in run()
1809 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; in run()
1811 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; in run()
1812 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n"; in run()
1814 OS << "namespace llvm {\n"; in run()
1816 OS << "namespace {\n"; in run()
1818 unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap); in run()
1819 OS << "\n"; in run()
1820 EmitSchedModel(OS); in run()
1821 OS << "\n"; in run()
1822 unsigned NumProcs = CPUKeyValues(OS, FeatureMap); in run()
1823 OS << "\n"; in run()
1825 OS << "} // end anonymous namespace\n\n"; in run()
1829 emitGenMCSubtargetInfo(OS); in run()
1831 OS << "\nstatic inline MCSubtargetInfo *create" << Target in run()
1834 OS << " return new " << Target in run()
1837 OS << Target << "FeatureKV, "; in run()
1839 OS << "None, "; in run()
1841 OS << Target << "SubTypeKV, "; in run()
1843 OS << "None, "; in run()
1844 OS << '\n'; OS.indent(22); in run()
1845 OS << Target << "WriteProcResTable, " in run()
1848 OS << '\n'; OS.indent(22); in run()
1850 OS << Target << "Stages, " in run()
1854 OS << "nullptr, nullptr, nullptr"; in run()
1855 OS << ");\n}\n\n"; in run()
1857 OS << "} // end namespace llvm\n\n"; in run()
1859 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n"; in run()
1861 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; in run()
1862 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n"; in run()
1864 OS << "#include \"llvm/Support/Debug.h\"\n"; in run()
1865 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; in run()
1866 ParseFeaturesFunction(OS, NumFeatures, NumProcs); in run()
1868 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; in run()
1871 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n"; in run()
1872 OS << "#undef GET_SUBTARGETINFO_HEADER\n\n"; in run()
1875 OS << "namespace llvm {\n"; in run()
1876 OS << "class DFAPacketizer;\n"; in run()
1877 OS << "namespace " << Target << "_MC {\n" in run()
1881 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" in run()
1894 OS << " unsigned getHwMode() const override;\n"; in run()
1899 PE.expandSTIPredicate(OS, Fn); in run()
1901 OS << "};\n" in run()
1904 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n"; in run()
1906 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n"; in run()
1907 OS << "#undef GET_SUBTARGETINFO_CTOR\n\n"; in run()
1909 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n"; in run()
1910 OS << "namespace llvm {\n"; in run()
1911 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; in run()
1912 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n"; in run()
1913 OS << "extern const llvm::MCWriteProcResEntry " in run()
1915 OS << "extern const llvm::MCWriteLatencyEntry " in run()
1917 OS << "extern const llvm::MCReadAdvanceEntry " in run()
1921 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; in run()
1922 OS << "extern const unsigned " << Target << "OperandCycles[];\n"; in run()
1923 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; in run()
1926 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, " in run()
1930 OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), "; in run()
1932 OS << "None, "; in run()
1934 OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), "; in run()
1936 OS << "None, "; in run()
1937 OS << '\n'; OS.indent(24); in run()
1938 OS << Target << "WriteProcResTable, " in run()
1941 OS << '\n'; OS.indent(24); in run()
1943 OS << Target << "Stages, " in run()
1947 OS << "nullptr, nullptr, nullptr"; in run()
1948 OS << ") {}\n\n"; in run()
1950 EmitSchedModelHelpers(ClassName, OS); in run()
1951 EmitHwModeCheck(ClassName, OS); in run()
1953 OS << "} // end namespace llvm\n\n"; in run()
1955 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; in run()
1957 EmitMCInstrAnalysisPredicateFunctions(OS); in run()
1962 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) { in EmitSubtarget() argument
1964 SubtargetEmitter(RK, CGTarget).run(OS); in EmitSubtarget()