Lines Matching refs:ModelDef
840 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
841 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
871 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
892 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
893 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
923 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1343 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " in EmitProcessorModels()
1349 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1350 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1351 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1352 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1353 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1354 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1357 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1363 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); in EmitProcessorModels()