Lines Matching refs:getName
119 << "extern const MCRegisterClass " << Target.getName() in runEnums()
127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
147 OS << " " << RC.getName() << "RegClassID" in runEnums()
163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
368 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) in finalizeDwarfRegNumsKeys()
377 return A.first->getName() == B.first->getName(); in finalizeDwarfRegNumsKeys()
825 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
904 RegStrings.add(std::string(Reg.getName())); in runMCDesc()
970 const std::string &TargetName = std::string(Target.getName()); in runMCDesc()
993 << Idx.getName() << "\n"; in runMCDesc()
1009 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
1045 const std::string &Name = RC.getName(); in runMCDesc()
1083 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1085 << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
1143 const std::string &TargetName = std::string(Target.getName()); in runTargetHeader()
1191 const std::string &Name = RC.getName(); in runTargetHeader()
1216 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1256 OS << Idx.getName(); in runTargetDesc()
1266 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1295 << RC.getName() << '\n'; in runTargetDesc()
1329 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1344 OS << "// " << Idx.getName(); in runTargetDesc()
1364 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1373 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1376 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1387 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1396 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1407 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1408 << "RegClass = {\n " << '&' << Target.getName() in runTargetDesc()
1409 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1410 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1421 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1425 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1440 const std::string &TargetName = std::string(Target.getName()); in runTargetDesc()
1488 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; in runTargetDesc()
1513 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1516 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1517 << " -> " << SRC->getName() << "\n"; in runTargetDesc()
1519 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1583 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1602 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1614 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1627 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1674 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1687 OS << " " << R->getName(); in debugDump()
1695 OS << " " << SRC.getName(); in debugDump()
1700 OS << " " << SRC->getName(); in debugDump()
1706 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1712 OS << "Register " << R.getName() << ":\n"; in debugDump()
1720 OS << "\tSubReg " << P.first->getName() in debugDump()
1721 << " = " << P.second->getName() << '\n'; in debugDump()