Lines Matching refs:RB
74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
396 const RegisterBank &RB, in getLoadStoreOp() argument
405 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
408 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
411 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
413 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
421 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
423 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); in selectLoadStoreOp()