464   Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();  in checkRegUsage()  local
477       if (TRI->regsOverlap(Reg, BaseReg)) {  in checkRegUsage()
516   Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();  in optLEAALU()  local
519     BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optLEAALU()
523     if (BaseReg == IndexReg)  in optLEAALU()
525     std::swap(BaseReg, IndexReg);  in optLEAALU()
528   if (BaseReg == IndexReg)  in optLEAALU()
537                .addReg(BaseReg, KilledBase ? RegState::Kill : 0);  in optLEAALU()
576   Register BaseReg = Base.getReg();  in optTwoAddrLEA()  local
585     if (BaseReg != 0)  in optTwoAddrLEA()
586       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optTwoAddrLEA()
596   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&  in optTwoAddrLEA()
597       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
599     if (DestReg != BaseReg)  in optTwoAddrLEA()
600       std::swap(BaseReg, IndexReg);  in optTwoAddrLEA()
605         .addReg(BaseReg).addReg(IndexReg)  in optTwoAddrLEA()
610         .addReg(BaseReg).addReg(IndexReg);  in optTwoAddrLEA()
612   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
627           .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);  in optTwoAddrLEA()
630           .addReg(BaseReg);  in optTwoAddrLEA()
637           .addReg(BaseReg).addImm(Disp.getImm())  in optTwoAddrLEA()
641           .addReg(BaseReg).addImm(Disp.getImm());  in optTwoAddrLEA()
644   } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {  in optTwoAddrLEA()
769   Register BaseReg = Base.getReg();  in processInstrForSlow3OpLEA()  local
773     if (BaseReg != 0)  in processInstrForSlow3OpLEA()
774       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in processInstrForSlow3OpLEA()
780   bool IsInefficientBase = isInefficientLEAReg(BaseReg);  in processInstrForSlow3OpLEA()
785   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
797   if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {  in processInstrForSlow3OpLEA()
799     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
800       std::swap(BaseReg, IndexReg);  in processInstrForSlow3OpLEA()
805                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
811                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
857   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
866     bool BIK = Base.isKill() && BaseReg != IndexReg;  in processInstrForSlow3OpLEA()
867     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()