426     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anonac1ae4a00111::X86AsmParser::IntelExprStateMachine
450         : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),  in IntelExprStateMachine()
459     unsigned getBaseReg() const { return BaseReg; }  in getBaseReg()
655           if (!BaseReg) {  in onPlus()
656             BaseReg = TmpReg;  in onPlus()
716           if (!BaseReg) {  in onMinus()
717             BaseReg = TmpReg;  in onMinus()
964           if (!BaseReg) {  in onRBrac()
965             BaseReg = TmpReg;  in onRBrac()
1122                                unsigned BaseReg, unsigned IndexReg,
1274 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1281   if (BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1282       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||  in CheckBaseRegAndIndexRegAndScale()
1283         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1284         X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1285         X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {  in CheckBaseRegAndIndexRegAndScale()
1302   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1311   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1312       (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&  in CheckBaseRegAndIndexRegAndScale()
1313                        BaseReg != X86::SI && BaseReg != X86::DI))) {  in CheckBaseRegAndIndexRegAndScale()
1318   if (BaseReg == 0 &&  in CheckBaseRegAndIndexRegAndScale()
1324   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1325     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1332     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1339     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexRegAndScale()
1345       if ((BaseReg != X86::BX && BaseReg != X86::BP) ||  in CheckBaseRegAndIndexRegAndScale()
1354   if (!Is64BitMode && BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1355       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {  in CheckBaseRegAndIndexRegAndScale()
1663         unsigned OrigReg = OrigOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1664         unsigned FinalReg = FinalOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1698         FinalOp.Mem.BaseReg = FinalReg;  in VerifyAndAdjustOperands()
1727     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1760   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForMSInlineAsm()
1768   BaseReg = BaseReg ? BaseReg : 1;  in CreateMemForMSInlineAsm()
1770       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2552   unsigned BaseReg = SM.getBaseReg();  in ParseIntelOperand()  local
2558   if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&  in ParseIntelOperand()
2560     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2568       (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||  in ParseIntelOperand()
2569        X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||  in ParseIntelOperand()
2570        X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))  in ParseIntelOperand()
2571     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2584   if ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in ParseIntelOperand()
2586     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2588   if ((BaseReg || IndexReg) &&  in ParseIntelOperand()
2589       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseIntelOperand()
2593     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2601                                              BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2607   if ((BaseReg || IndexReg || RegNo))  in ParseIntelOperand()
2609                                              BaseReg, IndexReg, Scale, Start,  in ParseIntelOperand()
2906   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2918     BaseReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2919     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)  in ParseMemOperand()
2947         if (BaseReg == X86::RIP)  in ParseMemOperand()
2965             if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
2983   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
2990   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
2994   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2996                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()