Lines Matching refs:atomic
40 "memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
41 "memory.atomic.notify \t${off}${p2align}", 0x00, "false">;
46 "memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
47 "memory.atomic.notify \t${off}${p2align}", 0x00, "true">;
54 "memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
55 "memory.atomic.wait32 \t${off}${p2align}", 0x01, "false">;
61 "memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
62 "memory.atomic.wait32 \t${off}${p2align}", 0x01, "true">;
68 "memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
69 "memory.atomic.wait64 \t${off}${p2align}", 0x02, "false">;
75 "memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
76 "memory.atomic.wait64 \t${off}${p2align}", 0x02, "true">;
213 defm ATOMIC_FENCE : ATOMIC_NRI<(outs), (ins i8imm:$flags), [], "atomic.fence",
226 defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
227 defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
249 // Extending loads. Note that there are only zero-extending atomic loads, no
251 defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
252 defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
253 defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>;
254 defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
255 defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
265 // Extension to i32 is elided by SelectionDAG as our atomic loads are
277 // We don't have single sext atomic load instructions. So for sext loads, we
296 // 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
315 // No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64
344 defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
345 defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
347 // We need an 'atomic' version of store patterns because store and atomic_store
405 defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>;
406 defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>;
407 defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>;
408 defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>;
409 defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>;
413 // We don't have single truncating atomic store instructions. For 32-bit
414 // instructions, we just need to match bare atomic stores. On the other hand,
481 defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>;
482 defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>;
484 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>;
486 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>;
488 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>;
490 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>;
492 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>;
494 defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>;
495 defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>;
497 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>;
499 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>;
501 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>;
503 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>;
505 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>;
507 defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>;
508 defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>;
510 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>;
512 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>;
514 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>;
516 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>;
518 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>;
520 defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>;
521 defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>;
523 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>;
525 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>;
527 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>;
529 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>;
531 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>;
533 defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>;
534 defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>;
536 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>;
538 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>;
540 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>;
542 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>;
544 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>;
547 WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>;
549 WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>;
551 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>;
553 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>;
555 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>;
557 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>;
559 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
658 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
781 WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>;
783 WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>;
785 WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>;
787 WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>;
789 WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>;
791 WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>;
793 WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
894 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s