Lines Matching refs:V2
1080 bits<5> V2;
1087 let Inst{35-32} = V2{3-0};
1093 let Inst{10} = V2{4};
1105 bits<5> V2;
1112 let Inst{35-32} = V2{3-0};
1117 let Inst{10} = V2{4};
1128 bits<5> V2;
1135 let Inst{35-32} = V2{3-0};
1141 let Inst{10} = V2{4};
1153 bits<5> V2;
1160 let Inst{35-32} = V2{3-0};
1165 let Inst{10} = V2{4};
1219 bits<5> V2;
1226 let Inst{35-32} = V2{3-0};
1235 let Inst{10} = V2{4};
1249 bits<5> V2;
1256 let Inst{35-32} = V2{3-0};
1266 let Inst{10} = V2{4};
1278 bits<5> V2;
1286 let Inst{35-32} = V2{3-0};
1293 let Inst{10} = V2{4};
1308 bits<5> V2;
1316 let Inst{35-32} = V2{3-0};
1326 let Inst{10} = V2{4};
1338 bits<5> V2;
1346 let Inst{35-32} = V2{3-0};
1353 let Inst{10} = V2{4};
1401 bits<5> V2;
1407 let Inst{31-28} = V2{3-0};
1413 let Inst{9} = V2{4};
1424 bits<5> V2;
1430 let Inst{35-32} = V2{3-0};
1436 let Inst{10} = V2{4};
1447 bits<5> V2;
1453 let Inst{35-32} = V2{3-0};
1460 let Inst{10} = V2{4};
1472 bits<5> V2;
1477 let Inst{35-32} = V2{3-0};
1484 let Inst{10} = V2{4};
3055 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
3056 mnemonic#"\t$V1, $V2",
3057 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> {
3067 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3068 mnemonic#"\t$V1, $V2, $M3", []> {
3075 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3076 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3090 (ins tr2.op:$V2, imm32zx4:$M5),
3091 mnemonic#"\t$V1, $V2, $M5", []>;
3092 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
3093 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
3094 def : InstAlias<mnemonic#"\t$V1, $V2",
3095 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
3104 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3105 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
3106 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
3107 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3678 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3679 mnemonic#"\t$V1, $V2, $I3",
3680 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3688 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3689 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
3698 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3699 mnemonic#"\t$V1, $V2, $M5",
3700 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3708 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3709 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3714 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3715 mnemonic#"\t$V1, $V2, $V3",
3716 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3723 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3724 mnemonic#"\t$V1, $V2, $V3, $M5", []> {
3730 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3731 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3748 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3749 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3763 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3764 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3765 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3766 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3767 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3768 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3777 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3778 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3779 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3780 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3787 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3788 mnemonic#"\t$V1, $V2, $V3",
3789 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3801 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3802 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3809 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3810 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3830 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3832 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
3841 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3842 mnemonic#"\t$R1, $V2, $M3", []> {
3847 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3848 mnemonic#"\t$V1, $V2, $M3", []>;
4152 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
4153 mnemonic#"\t$V1, $V2",
4154 [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> {
4164 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4165 mnemonic#"\t$V1, $V2, $M3", []> {
4173 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
4174 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
4180 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4181 mnemonic#"\t$V1, $V2, $M3", []> {
4421 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4422 mnemonic#"\t$V1, $V2, $V3, $I4",
4423 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4437 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
4438 mnemonic#"\t$V1, $V2, $M4, $M5",
4439 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4448 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4449 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4455 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4456 mnemonic#"\t$V1, $V2, $V3, $M5",
4457 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4474 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4475 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4480 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4481 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4488 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4489 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4490 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4491 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4498 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4499 mnemonic#"\t$V1, $V2, $V3, $M4",
4500 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4511 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4512 mnemonic#"\t$V1, $V2, $V3, $M6",
4513 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4522 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4524 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4529 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4530 mnemonic#"\t$V1, $V2, $V3, $V4",
4531 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4540 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4541 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4552 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4553 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>;
4554 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4556 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4557 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4558 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4565 (ins VR128:$V2, VR128:$V3, VR128:$V4,
4567 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4568 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4569 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4577 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4578 mnemonic#"\t$V1, $V2, $V3, $V4",
4579 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4590 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4591 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4607 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4609 mnemonic#"\t$R1, $V2, $M3, $M4", []>;
4612 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4614 mnemonic#"\t$V1, $V2, $V3, $M4", []>;
4652 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4653 mnemonic#"\t$V1, $V2, $V3, $I4",
4655 (tr2.vt tr2.op:$V2),
4665 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4667 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4674 (ins VR128:$V2, VR128:$V3,
4676 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4680 (ins VR128:$V2, imm32zx8:$I3,
4682 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>;
4689 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4690 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4691 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4701 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4702 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4715 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4716 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4722 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4723 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4730 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4731 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
5208 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
5209 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;