Lines Matching refs:Num

107     unsigned Num;  member
169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() argument
172 Op->Reg.Num = Num; in createReg()
227 return Reg.Num; in getReg()
404 unsigned Num; member
774 if (Name.substr(1).getAsInteger(10, Reg.Num)) { in parseRegister()
781 if (Prefix == 'r' && Reg.Num < 16) in parseRegister()
783 else if (Prefix == 'f' && Reg.Num < 16) in parseRegister()
785 else if (Prefix == 'v' && Reg.Num < 32) in parseRegister()
787 else if (Prefix == 'a' && Reg.Num < 16) in parseRegister()
789 else if (Prefix == 'c' && Reg.Num < 16) in parseRegister()
880 if (Regs[Reg.Num] == 0) { in parseRegister()
886 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc)); in parseRegister()
922 if (Reg.Num > 15) { in parseAnyRegister()
932 RegNo = SystemZMC::GR64Regs[Reg.Num]; in parseAnyRegister()
936 RegNo = SystemZMC::FP64Regs[Reg.Num]; in parseAnyRegister()
940 RegNo = SystemZMC::VR128Regs[Reg.Num]; in parseAnyRegister()
944 RegNo = SystemZMC::AR32Regs[Reg.Num]; in parseAnyRegister()
948 RegNo = SystemZMC::CR64Regs[Reg.Num]; in parseAnyRegister()
980 Reg.Num = (unsigned)Value; in parseIntegerRegister()
1125 Base = Regs[Reg1.Num]; in parseAddress()
1141 Index = Regs[Reg1.Num]; in parseAddress()
1143 Base = Regs[Reg1.Num]; in parseAddress()
1149 Base = Regs[Reg2.Num]; in parseAddress()
1157 Base = Regs[Reg2.Num]; in parseAddress()
1176 LengthReg = SystemZMC::GR64Regs[Reg1.Num]; in parseAddress()
1181 Base = Regs[Reg2.Num]; in parseAddress()
1190 Index = SystemZMC::VR128Regs[Reg1.Num]; in parseAddress()
1195 Base = Regs[Reg2.Num]; in parseAddress()
1331 RegNo = SystemZMC::GR64Regs[Reg.Num]; in ParseRegister()
1333 RegNo = SystemZMC::FP64Regs[Reg.Num]; in ParseRegister()
1335 RegNo = SystemZMC::VR128Regs[Reg.Num]; in ParseRegister()
1337 RegNo = SystemZMC::AR32Regs[Reg.Num]; in ParseRegister()
1339 RegNo = SystemZMC::CR64Regs[Reg.Num]; in ParseRegister()