50 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)  in RISCVInstrInfo()  function in RISCVInstrInfo
54 MCInst RISCVInstrInfo::getNop() const {  in getNop()
63 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
90 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
121 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
243 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
337 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
429 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,  in movImm()
505 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,  in analyzeBranch()
573 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
607 unsigned RISCVInstrInfo::insertBranch(  in insertBranch()
644 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
680 bool RISCVInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
688 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {  in getBranchDestBlock()
695 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
719 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
809 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {  in isAsCheapAsAMove()
830 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {  in isCopyInstrImpl()
853 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
904 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(  in getMemOperandWithOffsetWidth()
927 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(  in areMemAccessesTriviallyDisjoint()
959 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
965 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
982 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(  in isFunctionSafeToOutlineFrom()
999 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,  in isMBBSafeToOutlineFrom()
1010 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(  in getOutliningCandidateInfo()
1052 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,  in getOutliningType()
1100 void RISCVInstrInfo::buildOutlinedFrame(  in buildOutlinedFrame()
1128 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(  in insertOutlinedCall()
1159 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
1282 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,  in commuteInstructionImpl()
1412 MachineInstr *RISCVInstrInfo::convertToThreeAddress(  in convertToThreeAddress()
1466 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,  in getVLENFactoredAmount()
1477   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();  in getVLENFactoredAmount()
1566 bool RISCVInstrInfo::isRVVSpill(const MachineInstr &MI, bool CheckFIs) const {  in isRVVSpill()
1579 RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {  in isRVVSpillForZvlsseg()