Lines Matching refs:hasStdExtZfh

86   if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
132     if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
311   if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
314   if (Subtarget.hasStdExtZfh()) {  in RISCVTargetLowering()
641     if (Subtarget.hasStdExtZfh())  in RISCVTargetLowering()
999   if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())  in isFPImmLegal()
1011   return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||  in hasBitPreservingFPLogic()
1021   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getRegisterTypeForCallingConv()
1032   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getNumRegistersForCallingConv()
1241     if (!Subtarget.hasStdExtZfh())  in useRVVForFixedLengthVectorVT()
2151     if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {  in LowerOperation()
5087     if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) {  in ReplaceNodeResults()
8492       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)  in getRegForInlineAsmConstraint()
8891     return Subtarget.hasStdExtZfh();  in isFMAFasterThanFMulAndFAdd()