56       !Subtarget.hasStdExtF()) {  in RISCVTargetLowering()
88   if (Subtarget.hasStdExtF())  in RISCVTargetLowering()
136     if (Subtarget.hasStdExtF())  in RISCVTargetLowering()
330   if (Subtarget.hasStdExtF()) {  in RISCVTargetLowering()
348   if (Subtarget.hasStdExtF() && Subtarget.is64Bit())  in RISCVTargetLowering()
378   if (Subtarget.hasStdExtF()) {  in RISCVTargetLowering()
646       if (Subtarget.hasStdExtF())  in RISCVTargetLowering()
1001   if (VT == MVT::f32 && !Subtarget.hasStdExtF())  in isFPImmLegal()
1012          (VT == MVT::f32 && Subtarget.hasStdExtF()) ||  in hasBitPreservingFPLogic()
1021   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getRegisterTypeForCallingConv()
1032   if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh())  in getNumRegistersForCallingConv()
1245     if (!Subtarget.hasStdExtF())  in useRVVForFixedLengthVectorVT()
2157         Subtarget.hasStdExtF()) {  in LowerOperation()
5091                Subtarget.hasStdExtF()) {  in ReplaceNodeResults()
8494       if (Subtarget.hasStdExtF() && VT == MVT::f32)  in getRegForInlineAsmConstraint()
8560   if (Subtarget.hasStdExtF()) {  in getRegForInlineAsmConstraint()
8893     return Subtarget.hasStdExtF();  in isFMAFasterThanFMulAndFAdd()