45 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,  in RISCVTargetLowering()  function in RISCVTargetLowering
873 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,  in getSetCCResultType()
884 MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const {  in getVPExplicitVectorLengthTy()
888 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
917 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
943 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {  in isLegalICmpImmediate()
947 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {  in isLegalAddImmediate()
954 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {  in isTruncateFree()
962 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {  in isTruncateFree()
971 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
985 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {  in isSExtCheaperThanZExt()
989 bool RISCVTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
993 bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
997 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
1010 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {  in hasBitPreservingFPLogic()
1016 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,  in getRegisterTypeForCallingConv()
1027 unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,  in getNumRegistersForCallingConv()
1093 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) {  in getLMUL()
1119 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {  in getRegClassIDForLMUL()
1137 unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {  in getSubregIndexByMVT()
1160 unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {  in getRegClassIDForVecVT()
1172 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(  in decomposeSubvectorInsertExtractToSubRegs()
1204 bool RISCVTargetLowering::mergeStoresAfterLegalization(EVT VT) const {  in mergeStoresAfterLegalization()
1267 bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const {  in useRVVForFixedLengthVectorVT()
1309 MVT RISCVTargetLowering::getContainerForFixedLengthVector(MVT VT) const {  in getContainerForFixedLengthVector()
1369 bool RISCVTargetLowering::shouldExpandBuildVectorWithShuffles(  in shouldExpandBuildVectorWithShuffles()
1374 bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {  in isShuffleMaskLegal()
2033 SDValue RISCVTargetLowering::expandUnalignedRVVLoad(SDValue Op,  in expandUnalignedRVVLoad()
2062 SDValue RISCVTargetLowering::expandUnalignedRVVStore(SDValue Op,  in expandUnalignedRVVStore()
2089 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
2692 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,  in getAddr()
2732 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,  in lowerGlobalAddress()
2754 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,  in lowerBlockAddress()
2761 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,  in lowerConstantPool()
2768 SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,  in lowerJumpTable()
2775 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,  in getStaticTLSAddr()
2816 SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,  in getDynamicTLSAddr()
2848 SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,  in lowerGlobalTLSAddress()
2886 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in lowerSELECT()
2951 SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {  in lowerBRCOND()
2974 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {  in lowerVASTART()
2989 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,  in lowerFRAMEADDR()
3012 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,  in lowerRETURNADDR()
3042 SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,  in lowerShiftLeftParts()
3081 SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,  in lowerShiftRightParts()
3135 SDValue RISCVTargetLowering::lowerVectorMaskSplat(SDValue Op,  in lowerVectorMaskSplat()
3164 SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,  in lowerSPLAT_VECTOR_PARTS()
3210 SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,  in lowerVectorMaskExt()
3261 SDValue RISCVTargetLowering::lowerFixedLengthVectorExtendToRVV(  in lowerFixedLengthVectorExtendToRVV()
3292 SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,  in lowerVectorMaskTrunc()
3337 SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,  in lowerINSERT_VECTOR_ELT()
3434 SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,  in lowerEXTRACT_VECTOR_ELT()
3554 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
3711 SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,  in LowerINTRINSIC_W_CHAIN()
3747 SDValue RISCVTargetLowering::lowerVectorMaskVECREDUCE(SDValue Op,  in lowerVectorMaskVECREDUCE()
3793 SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,  in lowerVECREDUCE()
3870 SDValue RISCVTargetLowering::lowerFPVECREDUCE(SDValue Op,  in lowerFPVECREDUCE()
3901 SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,  in lowerINSERT_SUBVECTOR()
3982       RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(  in lowerINSERT_SUBVECTOR()
3985   RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecVT);  in lowerINSERT_SUBVECTOR()
4051 SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,  in lowerEXTRACT_SUBVECTOR()
4131       RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(  in lowerEXTRACT_SUBVECTOR()
4177 SDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,  in lowerSTEP_VECTOR()
4207 SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,  in lowerVECTOR_REVERSE()
4281 RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,  in lowerFixedLengthVectorLoadToRVV()
4307 RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,  in lowerFixedLengthVectorStoreToRVV()
4341 SDValue RISCVTargetLowering::lowerMLOAD(SDValue Op, SelectionDAG &DAG) const {  in lowerMLOAD()
4378 SDValue RISCVTargetLowering::lowerMSTORE(SDValue Op, SelectionDAG &DAG) const {  in lowerMSTORE()
4407 RISCVTargetLowering::lowerFixedLengthVectorSetccToRVV(SDValue Op,  in lowerFixedLengthVectorSetccToRVV()
4432 SDValue RISCVTargetLowering::lowerFixedLengthVectorLogicOpToRVV(  in lowerFixedLengthVectorLogicOpToRVV()
4443 RISCVTargetLowering::lowerFixedLengthVectorShiftToRVV(SDValue Op,  in lowerFixedLengthVectorShiftToRVV()
4457 SDValue RISCVTargetLowering::lowerABS(SDValue Op, SelectionDAG &DAG) const {  in lowerABS()
4481 SDValue RISCVTargetLowering::lowerFixedLengthVectorFCOPYSIGNToRVV(  in lowerFixedLengthVectorFCOPYSIGNToRVV()
4503 SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(  in lowerFixedLengthVectorSelectToRVV()
4528 SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,  in lowerToScalableOp()
4567 SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG,  in lowerVPOp()
4604 SDValue RISCVTargetLowering::lowerMGATHER(SDValue Op, SelectionDAG &DAG) const {  in lowerMGATHER()
4685 SDValue RISCVTargetLowering::lowerMSCATTER(SDValue Op,  in lowerMSCATTER()
4752 SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,  in lowerGET_ROUNDING()
4783 SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,  in lowerSET_ROUNDING()
4870 void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
5869 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
6364 bool RISCVTargetLowering::isDesirableToCommuteWithShift(  in isDesirableToCommuteWithShift()
6412 bool RISCVTargetLowering::targetShrinkDemandedConstant(  in targetShrinkDemandedConstant()
6512 void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,  in computeKnownBitsForTargetNode()
6613 unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
6936 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,  in EmitInstrWithCustomInserter()
7051                                CCState &State, const RISCVTargetLowering &TLI) {  in allocateRVVReg()
7074                      bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,  in CC_RISCV()
7296 void RISCVTargetLowering::analyzeInputArgs(  in analyzeInputArgs()
7328 void RISCVTargetLowering::analyzeOutputArgs(  in analyzeOutputArgs()
7382                                 const RISCVTargetLowering &TLI) {  in unpackFromRegLoc()
7496                             const RISCVTargetLowering &TLI,  in CC_RISCV_FastCC()
7638 SDValue RISCVTargetLowering::LowerFormalArguments(  in LowerFormalArguments()
7796 bool RISCVTargetLowering::isEligibleForTailCallOptimization(  in isEligibleForTailCallOptimization()
7873 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
8173 bool RISCVTargetLowering::CanLowerReturn(  in CanLowerReturn()
8196 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
8295 void RISCVTargetLowering::validateCCReservedRegs(  in validateCCReservedRegs()
8308 bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {  in mayBeEmittedAsTailCall()
8312 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
8459 RISCVTargetLowering::ConstraintType
8460 RISCVTargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
8482 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()
8660 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {  in getInlineAsmMemConstraint()
8674 void RISCVTargetLowering::LowerAsmOperandForConstraint(  in LowerAsmOperandForConstraint()
8721 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,  in emitLeadingFence()
8731 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,  in emitTrailingFence()
8740 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
8804 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(  in emitMaskedAtomicRMWIntrinsic()
8848 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
8856 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(  in emitMaskedAtomicCmpXchgIntrinsic()
8878 bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(EVT VT) const {  in shouldRemoveExtendFromGSIndex()
8882 bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,  in isFMAFasterThanFMulAndFAdd()
8903 Register RISCVTargetLowering::getExceptionPointerRegister(  in getExceptionPointerRegister()
8908 Register RISCVTargetLowering::getExceptionSelectorRegister(  in getExceptionSelectorRegister()
8913 bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {  in shouldExtendTypeInLibCall()
8923 bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {  in shouldSignExtendTypeInLibCall()
8930 bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,  in decomposeMulByConstant()
8962 bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(  in allowsMisalignedMemoryAccesses()
8978 bool RISCVTargetLowering::splitValueIntoRegisterParts(  in splitValueIntoRegisterParts()
9020 SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(  in joinRegisterPartsIntoValue()
9065 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,  in getRegisterByName()