Lines Matching refs:PPC
96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
111 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; in PPCRegisterInfo()
112 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; in PPCRegisterInfo()
113 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; in PPCRegisterInfo()
114 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; in PPCRegisterInfo()
115 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; in PPCRegisterInfo()
118 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX; in PPCRegisterInfo()
119 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX; in PPCRegisterInfo()
120 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX; in PPCRegisterInfo()
121 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX; in PPCRegisterInfo()
122 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; in PPCRegisterInfo()
123 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; in PPCRegisterInfo()
124 ImmToIdxMap[PPC::LXV] = PPC::LXVX; in PPCRegisterInfo()
125 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; in PPCRegisterInfo()
126 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; in PPCRegisterInfo()
127 ImmToIdxMap[PPC::STXV] = PPC::STXVX; in PPCRegisterInfo()
128 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; in PPCRegisterInfo()
129 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; in PPCRegisterInfo()
132 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; in PPCRegisterInfo()
133 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; in PPCRegisterInfo()
134 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; in PPCRegisterInfo()
135 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; in PPCRegisterInfo()
138 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX; in PPCRegisterInfo()
139 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX; in PPCRegisterInfo()
140 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX; in PPCRegisterInfo()
141 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX; in PPCRegisterInfo()
153 return &PPC::G8RC_NOX0RegClass; in getPointerRegClass()
154 return &PPC::GPRC_NOR0RegClass; in getPointerRegClass()
158 return &PPC::G8RCRegClass; in getPointerRegClass()
159 return &PPC::GPRCRegClass; in getPointerRegClass()
188 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) && in getCalleeSavedRegs()
283 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) in adjustStackMapLiveOutMask()
294 markSuperRegs(Reserved, PPC::ZERO); in getReservedRegs()
298 markSuperRegs(Reserved, PPC::FP); in getReservedRegs()
302 markSuperRegs(Reserved, PPC::BP); in getReservedRegs()
306 markSuperRegs(Reserved, PPC::CTR); in getReservedRegs()
307 markSuperRegs(Reserved, PPC::CTR8); in getReservedRegs()
309 markSuperRegs(Reserved, PPC::R1); in getReservedRegs()
310 markSuperRegs(Reserved, PPC::LR); in getReservedRegs()
311 markSuperRegs(Reserved, PPC::LR8); in getReservedRegs()
312 markSuperRegs(Reserved, PPC::RM); in getReservedRegs()
314 markSuperRegs(Reserved, PPC::VRSAVE); in getReservedRegs()
325 markSuperRegs(Reserved, PPC::R2); // System-reserved register in getReservedRegs()
326 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register in getReservedRegs()
332 markSuperRegs(Reserved, PPC::R2); // System-reserved register in getReservedRegs()
336 markSuperRegs(Reserved, PPC::R13); in getReservedRegs()
339 markSuperRegs(Reserved, PPC::R31); in getReservedRegs()
344 markSuperRegs(Reserved, PPC::R29); in getReservedRegs()
346 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
350 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
354 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), in getReservedRegs()
355 IE = PPC::VRRCRegClass.end(); I != IE; ++I) in getReservedRegs()
505 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints()
513 case PPC::BUILD_UACC: { in getRegAllocationHints()
516 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && in getRegAllocationHints()
519 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) && in getRegAllocationHints()
521 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0); in getRegAllocationHints()
539 case PPC::G8RC_NOX0RegClassID: in getRegPressureLimit()
540 case PPC::GPRC_NOR0RegClassID: in getRegPressureLimit()
541 case PPC::SPERCRegClassID: in getRegPressureLimit()
542 case PPC::G8RCRegClassID: in getRegPressureLimit()
543 case PPC::GPRCRegClassID: { in getRegPressureLimit()
547 case PPC::F4RCRegClassID: in getRegPressureLimit()
548 case PPC::F8RCRegClassID: in getRegPressureLimit()
549 case PPC::VSLRCRegClassID: in getRegPressureLimit()
551 case PPC::VFRCRegClassID: in getRegPressureLimit()
552 case PPC::VRRCRegClassID: { in getRegPressureLimit()
560 case PPC::VSFRCRegClassID: in getRegPressureLimit()
561 case PPC::VSSRCRegClassID: in getRegPressureLimit()
562 case PPC::VSRCRegClassID: { in getRegPressureLimit()
570 case PPC::CRRCRegClassID: in getRegPressureLimit()
590 RC == &PPC::G8RCRegClass) { in getLargestLegalSuperClass()
592 return &PPC::SPILLTOVSRRCRegClass; in getLargestLegalSuperClass()
594 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) in getLargestLegalSuperClass()
603 case PPC::VSSRCRegClassID: in getLargestLegalSuperClass()
605 case PPC::VSFRCRegClassID: in getLargestLegalSuperClass()
606 case PPC::VSRCRegClassID: in getLargestLegalSuperClass()
608 case PPC::VSRpRCRegClassID: in getLargestLegalSuperClass()
610 case PPC::ACCRCRegClassID: in getLargestLegalSuperClass()
611 case PPC::UACCRCRegClassID: in getLargestLegalSuperClass()
654 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc()
655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc()
664 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
666 .addReg(PPC::X1) in lowerDynamicAlloc()
668 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
669 .addReg(PPC::X1) in lowerDynamicAlloc()
672 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
674 .addReg(PPC::R1) in lowerDynamicAlloc()
676 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
677 .addReg(PPC::R1) in lowerDynamicAlloc()
720 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in prepareDynamicAlloca()
721 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca()
725 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) in prepareDynamicAlloca()
726 .addReg(PPC::X31) in prepareDynamicAlloca()
729 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
730 .addReg(PPC::R31) in prepareDynamicAlloca()
733 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) in prepareDynamicAlloca()
735 .addReg(PPC::X1); in prepareDynamicAlloca()
737 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer) in prepareDynamicAlloca()
739 .addReg(PPC::R1); in prepareDynamicAlloca()
749 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in prepareDynamicAlloca()
754 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in prepareDynamicAlloca()
766 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in prepareDynamicAlloca()
771 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in prepareDynamicAlloca()
796 const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR); in lowerPrepareProbedAlloca()
837 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), in lowerDynamicAreaOffset()
863 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling()
864 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling()
871 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRSpilling()
876 if (SrcReg != PPC::CR0) { in lowerCRSpilling()
881 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRSpilling()
888 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRSpilling()
908 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRRestore()
909 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore()
916 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
921 if (DestReg != PPC::CR0) { in lowerCRRestore()
927 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRRestore()
932 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) in lowerCRRestore()
952 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitSpilling()
953 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitSpilling()
988 case PPC::CRUNSET: in lowerCRBitSpilling()
989 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg) in lowerCRBitSpilling()
993 case PPC::CRSET: in lowerCRBitSpilling()
994 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg) in lowerCRBitSpilling()
1004 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg) in lowerCRBitSpilling()
1014 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT || in lowerCRBitSpilling()
1015 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT || in lowerCRBitSpilling()
1016 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT || in lowerCRBitSpilling()
1017 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) { in lowerCRBitSpilling()
1018 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg) in lowerCRBitSpilling()
1029 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRBitSpilling()
1040 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRBitSpilling()
1045 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRBitSpilling()
1053 Ins->setDesc(TII.get(PPC::UNENCODED_NOP)); in lowerCRBitSpilling()
1070 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitRestore()
1071 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitRestore()
1078 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
1084 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) in lowerCRBitRestore()
1089 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) in lowerCRBitRestore()
1096 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), in lowerCRBitRestore()
1114 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc"; in emitAccCopyInfo()
1115 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc"; in emitAccCopyInfo()
1151 bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg); in lowerACCSpilling()
1153 PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; in lowerACCSpilling()
1163 BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in lowerACCSpilling()
1164 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) in lowerACCSpilling()
1167 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) in lowerACCSpilling()
1171 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in lowerACCSpilling()
1191 bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg); in lowerACCRestore()
1193 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; in lowerACCRestore()
1200 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg), in lowerACCRestore()
1202 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1), in lowerACCRestore()
1205 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg); in lowerACCRestore()
1224 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2; in lowerQuadwordSpilling()
1227 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) in lowerQuadwordSpilling()
1230 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) in lowerQuadwordSpilling()
1252 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2; in lowerQuadwordRestore()
1255 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex, in lowerQuadwordRestore()
1257 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex, in lowerQuadwordRestore()
1274 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) { in hasReservedSpillSlot()
1286 case PPC::LWA: in offsetMinAlignForOpcode()
1287 case PPC::LWA_32: in offsetMinAlignForOpcode()
1288 case PPC::LD: in offsetMinAlignForOpcode()
1289 case PPC::LDU: in offsetMinAlignForOpcode()
1290 case PPC::STD: in offsetMinAlignForOpcode()
1291 case PPC::STDU: in offsetMinAlignForOpcode()
1292 case PPC::DFLOADf32: in offsetMinAlignForOpcode()
1293 case PPC::DFLOADf64: in offsetMinAlignForOpcode()
1294 case PPC::DFSTOREf32: in offsetMinAlignForOpcode()
1295 case PPC::DFSTOREf64: in offsetMinAlignForOpcode()
1296 case PPC::LXSD: in offsetMinAlignForOpcode()
1297 case PPC::LXSSP: in offsetMinAlignForOpcode()
1298 case PPC::STXSD: in offsetMinAlignForOpcode()
1299 case PPC::STXSSP: in offsetMinAlignForOpcode()
1300 case PPC::STQ: in offsetMinAlignForOpcode()
1302 case PPC::EVLDD: in offsetMinAlignForOpcode()
1303 case PPC::EVSTDD: in offsetMinAlignForOpcode()
1305 case PPC::LXV: in offsetMinAlignForOpcode()
1306 case PPC::STXV: in offsetMinAlignForOpcode()
1307 case PPC::LQ: in offsetMinAlignForOpcode()
1308 case PPC::LXVP: in offsetMinAlignForOpcode()
1309 case PPC::STXVP: in offsetMinAlignForOpcode()
1365 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { in eliminateFrameIndex()
1372 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { in eliminateFrameIndex()
1378 (OpC == PPC::PREPARE_PROBED_ALLOCA_64 || in eliminateFrameIndex()
1379 OpC == PPC::PREPARE_PROBED_ALLOCA_32 || in eliminateFrameIndex()
1380 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 || in eliminateFrameIndex()
1381 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) { in eliminateFrameIndex()
1387 if (OpC == PPC::SPILL_CR) { in eliminateFrameIndex()
1390 } else if (OpC == PPC::RESTORE_CR) { in eliminateFrameIndex()
1393 } else if (OpC == PPC::SPILL_CRBIT) { in eliminateFrameIndex()
1396 } else if (OpC == PPC::RESTORE_CRBIT) { in eliminateFrameIndex()
1399 } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) { in eliminateFrameIndex()
1402 } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) { in eliminateFrameIndex()
1405 } else if (OpC == PPC::SPILL_QUADWORD) { in eliminateFrameIndex()
1408 } else if (OpC == PPC::RESTORE_QUADWORD) { in eliminateFrameIndex()
1439 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) && in eliminateFrameIndex()
1442 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP; in eliminateFrameIndex()
1453 assert(OpC != PPC::DBG_VALUE && in eliminateFrameIndex()
1457 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ? in eliminateFrameIndex()
1460 if (OpC == PPC::PLXVP || OpC == PPC::PSTXVP) in eliminateFrameIndex()
1474 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in eliminateFrameIndex()
1475 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in eliminateFrameIndex()
1482 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1485 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) in eliminateFrameIndex()
1487 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1520 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
1522 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; in getFrameRegister()
1531 return PPC::X30; in getBaseRegister()
1534 return PPC::R29; in getBaseRegister()
1536 return PPC::R30; in getBaseRegister()
1573 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1603 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
1662 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm in isFrameOffsetLegal()