Lines Matching refs:PPC
91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
103 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
104 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
122 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
126 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
127 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
183 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
184 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
186 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
187 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
199 case PPC::DIR_7400: in getOperandLatency()
200 case PPC::DIR_750: in getOperandLatency()
201 case PPC::DIR_970: in getOperandLatency()
202 case PPC::DIR_E5500: in getOperandLatency()
203 case PPC::DIR_PWR4: in getOperandLatency()
204 case PPC::DIR_PWR5: in getOperandLatency()
205 case PPC::DIR_PWR5X: in getOperandLatency()
206 case PPC::DIR_PWR6: in getOperandLatency()
207 case PPC::DIR_PWR6X: in getOperandLatency()
208 case PPC::DIR_PWR7: in getOperandLatency()
209 case PPC::DIR_PWR8: in getOperandLatency()
256 case PPC::FADD: in isAssociativeAndCommutative()
257 case PPC::FADDS: in isAssociativeAndCommutative()
259 case PPC::FMUL: in isAssociativeAndCommutative()
260 case PPC::FMULS: in isAssociativeAndCommutative()
262 case PPC::VADDFP: in isAssociativeAndCommutative()
264 case PPC::XSADDDP: in isAssociativeAndCommutative()
265 case PPC::XVADDDP: in isAssociativeAndCommutative()
266 case PPC::XVADDSP: in isAssociativeAndCommutative()
267 case PPC::XSADDSP: in isAssociativeAndCommutative()
269 case PPC::XSMULDP: in isAssociativeAndCommutative()
270 case PPC::XVMULDP: in isAssociativeAndCommutative()
271 case PPC::XVMULSP: in isAssociativeAndCommutative()
272 case PPC::XSMULSP: in isAssociativeAndCommutative()
277 case PPC::MULHD: in isAssociativeAndCommutative()
278 case PPC::MULLD: in isAssociativeAndCommutative()
279 case PPC::MULHW: in isAssociativeAndCommutative()
280 case PPC::MULLW: in isAssociativeAndCommutative()
303 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
304 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
305 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
306 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
307 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
308 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
451 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP) in getFMAPatterns()
595 if (Operand.getReg() == PPC::ZERO8) { in finalizeInsInstrs()
668 *MBB->getParent(), PPC::RegisterPressureSets::VSSRC); in shouldReduceRegisterPressure()
671 return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] > in shouldReduceRegisterPressure()
699 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); in generateLoadForNewConst()
701 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1) in generateLoadForNewConst()
702 .addReg(PPC::X2) in generateLoadForNewConst()
711 LoadOpcode = PPC::DFLOADf32; in generateLoadForNewConst()
713 LoadOpcode = PPC::DFLOADf64; in generateLoadForNewConst()
1022 .addReg(PPC::ZERO8); in reassociateFMA()
1059 case PPC::EXTSW: in isCoalescableExtInstr()
1060 case PPC::EXTSW_32: in isCoalescableExtInstr()
1061 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
1064 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
1097 case PPC::LI: in isReallyTriviallyReMaterializable()
1098 case PPC::LI8: in isReallyTriviallyReMaterializable()
1099 case PPC::PLI: in isReallyTriviallyReMaterializable()
1100 case PPC::PLI8: in isReallyTriviallyReMaterializable()
1101 case PPC::LIS: in isReallyTriviallyReMaterializable()
1102 case PPC::LIS8: in isReallyTriviallyReMaterializable()
1103 case PPC::ADDIStocHA: in isReallyTriviallyReMaterializable()
1104 case PPC::ADDIStocHA8: in isReallyTriviallyReMaterializable()
1105 case PPC::ADDItocL: in isReallyTriviallyReMaterializable()
1106 case PPC::LOAD_STACK_GUARD: in isReallyTriviallyReMaterializable()
1107 case PPC::XXLXORz: in isReallyTriviallyReMaterializable()
1108 case PPC::XXLXORspz: in isReallyTriviallyReMaterializable()
1109 case PPC::XXLXORdpz: in isReallyTriviallyReMaterializable()
1110 case PPC::XXLEQVOnes: in isReallyTriviallyReMaterializable()
1111 case PPC::XXSPLTI32DX: in isReallyTriviallyReMaterializable()
1112 case PPC::V_SET0B: in isReallyTriviallyReMaterializable()
1113 case PPC::V_SET0H: in isReallyTriviallyReMaterializable()
1114 case PPC::V_SET0: in isReallyTriviallyReMaterializable()
1115 case PPC::V_SETALLONESB: in isReallyTriviallyReMaterializable()
1116 case PPC::V_SETALLONESH: in isReallyTriviallyReMaterializable()
1117 case PPC::V_SETALLONES: in isReallyTriviallyReMaterializable()
1118 case PPC::CRSET: in isReallyTriviallyReMaterializable()
1119 case PPC::CRUNSET: in isReallyTriviallyReMaterializable()
1120 case PPC::XXSETACCZ: in isReallyTriviallyReMaterializable()
1148 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec) in commuteInstructionImpl()
1233 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
1249 default: Opcode = PPC::NOP; break; in insertNoop()
1250 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
1251 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1252 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
1254 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1264 Nop.setOpcode(PPC::NOP); in getNop()
1289 if (I->getOpcode() == PPC::B && in analyzeBranch()
1305 if (LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1310 } else if (LastInst.getOpcode() == PPC::BCC) { in analyzeBranch()
1318 } else if (LastInst.getOpcode() == PPC::BC) { in analyzeBranch()
1323 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1326 } else if (LastInst.getOpcode() == PPC::BCn) { in analyzeBranch()
1331 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1334 } else if (LastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1335 LastInst.getOpcode() == PPC::BDNZ) { in analyzeBranch()
1342 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1345 } else if (LastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1346 LastInst.getOpcode() == PPC::BDZ) { in analyzeBranch()
1353 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1370 if (SecondLastInst.getOpcode() == PPC::BCC && in analyzeBranch()
1371 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1380 } else if (SecondLastInst.getOpcode() == PPC::BC && in analyzeBranch()
1381 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1386 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1390 } else if (SecondLastInst.getOpcode() == PPC::BCn && in analyzeBranch()
1391 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1396 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1400 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1401 SecondLastInst.getOpcode() == PPC::BDNZ) && in analyzeBranch()
1402 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1410 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1414 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1415 SecondLastInst.getOpcode() == PPC::BDZ) && in analyzeBranch()
1416 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1424 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1432 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1454 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in removeBranch()
1455 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1456 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1457 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1467 if (I->getOpcode() != PPC::BCC && in removeBranch()
1468 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1469 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1470 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1495 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in insertBranch()
1496 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1498 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1499 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1500 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1501 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1502 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1503 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1505 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1513 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1515 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1516 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1517 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1518 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1519 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1520 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1522 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1526 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in insertBranch()
1541 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
1552 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1553 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1554 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1555 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1583 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1584 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1586 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1587 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1590 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
1591 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
1596 case PPC::PRED_EQ: in insertSelect()
1597 case PPC::PRED_EQ_MINUS: in insertSelect()
1598 case PPC::PRED_EQ_PLUS: in insertSelect()
1599 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
1600 case PPC::PRED_NE: in insertSelect()
1601 case PPC::PRED_NE_MINUS: in insertSelect()
1602 case PPC::PRED_NE_PLUS: in insertSelect()
1603 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
1604 case PPC::PRED_LT: in insertSelect()
1605 case PPC::PRED_LT_MINUS: in insertSelect()
1606 case PPC::PRED_LT_PLUS: in insertSelect()
1607 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
1608 case PPC::PRED_GE: in insertSelect()
1609 case PPC::PRED_GE_MINUS: in insertSelect()
1610 case PPC::PRED_GE_PLUS: in insertSelect()
1611 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
1612 case PPC::PRED_GT: in insertSelect()
1613 case PPC::PRED_GT_MINUS: in insertSelect()
1614 case PPC::PRED_GT_PLUS: in insertSelect()
1615 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
1616 case PPC::PRED_LE: in insertSelect()
1617 case PPC::PRED_LE_MINUS: in insertSelect()
1618 case PPC::PRED_LE_PLUS: in insertSelect()
1619 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
1620 case PPC::PRED_UN: in insertSelect()
1621 case PPC::PRED_UN_MINUS: in insertSelect()
1622 case PPC::PRED_UN_PLUS: in insertSelect()
1623 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
1624 case PPC::PRED_NU: in insertSelect()
1625 case PPC::PRED_NU_MINUS: in insertSelect()
1626 case PPC::PRED_NU_PLUS: in insertSelect()
1627 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
1628 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
1629 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
1638 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1639 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1642 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
1656 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
1657 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
1658 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
1659 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
1661 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
1662 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
1663 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
1664 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
1666 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
1667 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
1668 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
1669 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
1671 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
1672 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
1673 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
1674 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
1688 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
1689 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
1691 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1697 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
1698 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
1700 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1709 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
1710 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1712 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1716 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
1722 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
1723 (PPC::G8RCRegClass.contains(DestReg) || in copyPhysReg()
1724 PPC::GPRCRegClass.contains(DestReg))) { in copyPhysReg()
1725 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg); in copyPhysReg()
1726 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
1727 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM; in copyPhysReg()
1740 } else if (PPC::G8RCRegClass.contains(SrcReg) && in copyPhysReg()
1741 PPC::VSFRCRegClass.contains(DestReg)) { in copyPhysReg()
1744 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1748 } else if (PPC::VSFRCRegClass.contains(SrcReg) && in copyPhysReg()
1749 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
1752 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1755 } else if (PPC::SPERCRegClass.contains(SrcReg) && in copyPhysReg()
1756 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1757 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); in copyPhysReg()
1760 } else if (PPC::GPRCRegClass.contains(SrcReg) && in copyPhysReg()
1761 PPC::SPERCRegClass.contains(DestReg)) { in copyPhysReg()
1762 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); in copyPhysReg()
1768 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1769 Opc = PPC::OR; in copyPhysReg()
1770 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1771 Opc = PPC::OR8; in copyPhysReg()
1772 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1773 Opc = PPC::FMR; in copyPhysReg()
1774 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1775 Opc = PPC::MCRF; in copyPhysReg()
1776 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1777 Opc = PPC::VOR; in copyPhysReg()
1778 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1787 Opc = PPC::XXLOR; in copyPhysReg()
1788 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
1789 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1790 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
1792 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
1793 if (SrcReg > PPC::VSRp15) in copyPhysReg()
1794 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2; in copyPhysReg()
1796 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; in copyPhysReg()
1797 if (DestReg > PPC::VSRp15) in copyPhysReg()
1798 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2; in copyPhysReg()
1800 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2; in copyPhysReg()
1801 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg). in copyPhysReg()
1803 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1). in copyPhysReg()
1807 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1808 Opc = PPC::CROR; in copyPhysReg()
1809 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1810 Opc = PPC::EVOR; in copyPhysReg()
1811 else if ((PPC::ACCRCRegClass.contains(DestReg) || in copyPhysReg()
1812 PPC::UACCRCRegClass.contains(DestReg)) && in copyPhysReg()
1813 (PPC::ACCRCRegClass.contains(SrcReg) || in copyPhysReg()
1814 PPC::UACCRCRegClass.contains(SrcReg))) { in copyPhysReg()
1820 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg); in copyPhysReg()
1821 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg); in copyPhysReg()
1823 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1825 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1827 BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1829 BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx) in copyPhysReg()
1833 BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg); in copyPhysReg()
1835 BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1837 } else if (PPC::G8pRCRegClass.contains(DestReg) && in copyPhysReg()
1838 PPC::G8pRCRegClass.contains(SrcReg)) { in copyPhysReg()
1840 unsigned DestRegIdx = DestReg - PPC::G8p0; in copyPhysReg()
1841 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx; in copyPhysReg()
1842 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1; in copyPhysReg()
1843 unsigned SrcRegIdx = SrcReg - PPC::G8p0; in copyPhysReg()
1844 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx; in copyPhysReg()
1845 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1; in copyPhysReg()
1846 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub0) in copyPhysReg()
1849 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub1) in copyPhysReg()
1867 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1868 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1870 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1871 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1873 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1875 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1877 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1879 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1881 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1883 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1885 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1887 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1889 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1891 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1893 } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1897 } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1901 } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1905 } else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1939 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1940 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
1994 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
1995 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in LoadRegFromStackSlot()
2047 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
2051 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
2062 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in onlyFoldImmediate()
2098 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in onlyFoldImmediate()
2099 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in onlyFoldImmediate()
2112 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2114 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2115 PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2136 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) in MBBDefinesCTR()
2173 if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF) in isSchedulingBoundary()
2181 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
2182 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2184 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2185 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
2190 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2191 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2193 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2194 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2197 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2204 } else if (OpC == PPC::B) { in PredicateInstruction()
2205 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2207 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2208 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
2213 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2217 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2221 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2225 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2233 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2241 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL || in PredicateInstruction()
2242 OpC == PPC::BCTRL8) { in PredicateInstruction()
2243 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
2246 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; in PredicateInstruction()
2249 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2250 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2251 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
2253 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2254 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
2255 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
2258 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
2259 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
2268 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit) in PredicateInstruction()
2269 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2282 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
2284 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
2291 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
2292 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
2298 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
2299 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2301 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
2302 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2318 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in ClobbersPredicate()
2319 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in ClobbersPredicate()
2352 case PPC::CMPWI: in analyzeCompare()
2353 case PPC::CMPLWI: in analyzeCompare()
2354 case PPC::CMPDI: in analyzeCompare()
2355 case PPC::CMPLDI: in analyzeCompare()
2361 case PPC::CMPW: in analyzeCompare()
2362 case PPC::CMPLW: in analyzeCompare()
2363 case PPC::CMPD: in analyzeCompare()
2364 case PPC::CMPLD: in analyzeCompare()
2365 case PPC::FCMPUS: in analyzeCompare()
2366 case PPC::FCMPUD: in analyzeCompare()
2386 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
2399 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
2400 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
2401 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
2441 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2442 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2443 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2445 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE) in optimizeCompareInstr()
2447 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2448 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2450 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
2475 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
2504 if (UseMI->getOpcode() != PPC::BCC) in optimizeCompareInstr()
2507 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2508 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2509 unsigned PredHint = PPC::getPredicateHint(Pred); in optimizeCompareInstr()
2514 if (Immed == -1 && PredCond == PPC::PRED_GT) in optimizeCompareInstr()
2517 Pred = PPC::getPredicate(PPC::PRED_GE, PredHint); in optimizeCompareInstr()
2518 else if (Immed == -1 && PredCond == PPC::PRED_LE) in optimizeCompareInstr()
2520 Pred = PPC::getPredicate(PPC::PRED_LT, PredHint); in optimizeCompareInstr()
2521 else if (Immed == 1 && PredCond == PPC::PRED_LT) in optimizeCompareInstr()
2523 Pred = PPC::getPredicate(PPC::PRED_LE, PredHint); in optimizeCompareInstr()
2524 else if (Immed == 1 && PredCond == PPC::PRED_GE) in optimizeCompareInstr()
2526 Pred = PPC::getPredicate(PPC::PRED_GT, PredHint); in optimizeCompareInstr()
2543 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
2544 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
2553 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
2554 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
2555 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
2578 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec || in optimizeCompareInstr()
2579 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec) in optimizeCompareInstr()
2582 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
2583 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
2600 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) && in optimizeCompareInstr()
2625 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2626 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2627 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2629 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && in optimizeCompareInstr()
2633 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
2634 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2635 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2637 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
2640 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
2641 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
2642 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
2643 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
2662 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
2666 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
2678 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) { in optimizeCompareInstr()
2693 NewOpC = MIOpC == PPC::RLWINM in optimizeCompareInstr()
2694 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec) in optimizeCompareInstr()
2695 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec); in optimizeCompareInstr()
2703 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec; in optimizeCompareInstr()
2712 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
2716 NewOpC = PPC::ANDI8_rec; in optimizeCompareInstr()
2739 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
2791 case PPC::STD: in isClusterableLdStOpcPair()
2792 case PPC::STFD: in isClusterableLdStOpcPair()
2793 case PPC::STXSD: in isClusterableLdStOpcPair()
2794 case PPC::DFSTOREf64: in isClusterableLdStOpcPair()
2799 case PPC::STW: in isClusterableLdStOpcPair()
2800 case PPC::STW8: in isClusterableLdStOpcPair()
2801 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8; in isClusterableLdStOpcPair()
2866 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) { in getInstSizeInBytes()
2930 case PPC::DFLOADf32: in expandVSXMemPseudo()
2931 UpperOpcode = PPC::LXSSP; in expandVSXMemPseudo()
2932 LowerOpcode = PPC::LFS; in expandVSXMemPseudo()
2934 case PPC::DFLOADf64: in expandVSXMemPseudo()
2935 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
2936 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
2938 case PPC::DFSTOREf32: in expandVSXMemPseudo()
2939 UpperOpcode = PPC::STXSSP; in expandVSXMemPseudo()
2940 LowerOpcode = PPC::STFS; in expandVSXMemPseudo()
2942 case PPC::DFSTOREf64: in expandVSXMemPseudo()
2943 UpperOpcode = PPC::STXSD; in expandVSXMemPseudo()
2944 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
2946 case PPC::XFLOADf32: in expandVSXMemPseudo()
2947 UpperOpcode = PPC::LXSSPX; in expandVSXMemPseudo()
2948 LowerOpcode = PPC::LFSX; in expandVSXMemPseudo()
2950 case PPC::XFLOADf64: in expandVSXMemPseudo()
2951 UpperOpcode = PPC::LXSDX; in expandVSXMemPseudo()
2952 LowerOpcode = PPC::LFDX; in expandVSXMemPseudo()
2954 case PPC::XFSTOREf32: in expandVSXMemPseudo()
2955 UpperOpcode = PPC::STXSSPX; in expandVSXMemPseudo()
2956 LowerOpcode = PPC::STFSX; in expandVSXMemPseudo()
2958 case PPC::XFSTOREf64: in expandVSXMemPseudo()
2959 UpperOpcode = PPC::STXSDX; in expandVSXMemPseudo()
2960 LowerOpcode = PPC::STFDX; in expandVSXMemPseudo()
2962 case PPC::LIWAX: in expandVSXMemPseudo()
2963 UpperOpcode = PPC::LXSIWAX; in expandVSXMemPseudo()
2964 LowerOpcode = PPC::LFIWAX; in expandVSXMemPseudo()
2966 case PPC::LIWZX: in expandVSXMemPseudo()
2967 UpperOpcode = PPC::LXSIWZX; in expandVSXMemPseudo()
2968 LowerOpcode = PPC::LFIWZX; in expandVSXMemPseudo()
2970 case PPC::STIWX: in expandVSXMemPseudo()
2971 UpperOpcode = PPC::STXSIWX; in expandVSXMemPseudo()
2972 LowerOpcode = PPC::STFIWX; in expandVSXMemPseudo()
2980 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2981 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
2998 case PPC::BUILD_UACC: { in expandPostRAPseudo()
3001 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { in expandPostRAPseudo()
3002 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4; in expandPostRAPseudo()
3003 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4; in expandPostRAPseudo()
3008 BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo) in expandPostRAPseudo()
3017 case PPC::KILL_PAIR: { in expandPostRAPseudo()
3018 MI.setDesc(get(PPC::UNENCODED_NOP)); in expandPostRAPseudo()
3027 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3028 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
3034 case PPC::DFLOADf32: in expandPostRAPseudo()
3035 case PPC::DFLOADf64: in expandPostRAPseudo()
3036 case PPC::DFSTOREf32: in expandPostRAPseudo()
3037 case PPC::DFSTOREf64: { in expandPostRAPseudo()
3045 case PPC::XFLOADf32: in expandPostRAPseudo()
3046 case PPC::XFSTOREf32: in expandPostRAPseudo()
3047 case PPC::LIWAX: in expandPostRAPseudo()
3048 case PPC::LIWZX: in expandPostRAPseudo()
3049 case PPC::STIWX: { in expandPostRAPseudo()
3056 case PPC::XFLOADf64: in expandPostRAPseudo()
3057 case PPC::XFSTOREf64: { in expandPostRAPseudo()
3064 case PPC::SPILLTOVSR_LD: { in expandPostRAPseudo()
3066 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3067 MI.setDesc(get(PPC::DFLOADf64)); in expandPostRAPseudo()
3071 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3074 case PPC::SPILLTOVSR_ST: { in expandPostRAPseudo()
3076 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3078 MI.setDesc(get(PPC::DFSTOREf64)); in expandPostRAPseudo()
3082 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3086 case PPC::SPILLTOVSR_LDX: { in expandPostRAPseudo()
3088 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
3089 MI.setDesc(get(PPC::LXSDX)); in expandPostRAPseudo()
3091 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3094 case PPC::SPILLTOVSR_STX: { in expandPostRAPseudo()
3096 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3098 MI.setDesc(get(PPC::STXSDX)); in expandPostRAPseudo()
3101 MI.setDesc(get(PPC::STDX)); in expandPostRAPseudo()
3106 case PPC::CFENCE8: { in expandPostRAPseudo()
3108 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
3109 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) in expandPostRAPseudo()
3110 .addImm(PPC::PRED_NE_MINUS) in expandPostRAPseudo()
3111 .addReg(PPC::CR7) in expandPostRAPseudo()
3113 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
3129 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) { in selectReg()
3132 case PPC::sub_lt: in selectReg()
3134 case PPC::sub_gt: in selectReg()
3136 case PPC::sub_eq: in selectReg()
3141 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) { in selectReg()
3144 case PPC::sub_lt: in selectReg()
3146 case PPC::sub_gt: in selectReg()
3148 case PPC::sub_eq: in selectReg()
3152 return PPC::NoRegister; in selectReg()
3195 MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in replaceInstrWithLI()
3198 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
3202 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI)); in replaceInstrWithLI()
3247 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 || in getForwardingDefMI()
3248 DefMI->getOpcode() == PPC::ADDI || in getForwardingDefMI()
3249 DefMI->getOpcode() == PPC::ADDI8) { in getForwardingDefMI()
3255 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3267 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI || in getForwardingDefMI()
3268 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
3269 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
3270 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec || in getForwardingDefMI()
3271 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 || in getForwardingDefMI()
3272 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 || in getForwardingDefMI()
3273 Opc == PPC::RLWINM8_rec; in getForwardingDefMI()
3281 if ((Opc == PPC::OR || Opc == PPC::OR8) && in getForwardingDefMI()
3298 case PPC::LI: in getForwardingDefMI()
3299 case PPC::LI8: in getForwardingDefMI()
3300 case PPC::ADDItocL: in getForwardingDefMI()
3301 case PPC::ADDI: in getForwardingDefMI()
3302 case PPC::ADDI8: in getForwardingDefMI()
3506 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0)) in foldFrameOffset()
3549 if (Opc != PPC::ADDI && Opc != PPC::ADDI8) in isADDIInstrEligibleForFolding()
3565 return Opc == PPC::ADD4 || Opc == PPC::ADD8; in isADDInstrEligibleForFolding()
3582 if (XFormOpcode == PPC::INSTRUCTION_LIST_END) in isImmInstrEligibleForFolding()
3677 PPC::INSTRUCTION_LIST_END && in convertToImmediateForm()
3715 if (SrcMI->getOpcode() != PPC::RLWINM && in combineRLWINM()
3716 SrcMI->getOpcode() != PPC::RLWINM_rec && in combineRLWINM()
3717 SrcMI->getOpcode() != PPC::RLWINM8 && in combineRLWINM()
3718 SrcMI->getOpcode() != PPC::RLWINM8_rec) in combineRLWINM()
3775 (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec); in combineRLWINM()
3780 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { in combineRLWINM()
3786 MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI)); in combineRLWINM()
3792 MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in combineRLWINM()
3859 case PPC::ADD4: in instrHasImmForm()
3860 case PPC::ADD8: in instrHasImmForm()
3866 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
3868 case PPC::ADDC: in instrHasImmForm()
3869 case PPC::ADDC8: in instrHasImmForm()
3875 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8; in instrHasImmForm()
3877 case PPC::ADDC_rec: in instrHasImmForm()
3883 III.ImmOpcode = PPC::ADDIC_rec; in instrHasImmForm()
3885 case PPC::SUBFC: in instrHasImmForm()
3886 case PPC::SUBFC8: in instrHasImmForm()
3891 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8; in instrHasImmForm()
3893 case PPC::CMPW: in instrHasImmForm()
3894 case PPC::CMPD: in instrHasImmForm()
3899 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI; in instrHasImmForm()
3901 case PPC::CMPLW: in instrHasImmForm()
3902 case PPC::CMPLD: in instrHasImmForm()
3907 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI; in instrHasImmForm()
3909 case PPC::AND_rec: in instrHasImmForm()
3910 case PPC::AND8_rec: in instrHasImmForm()
3911 case PPC::OR: in instrHasImmForm()
3912 case PPC::OR8: in instrHasImmForm()
3913 case PPC::XOR: in instrHasImmForm()
3914 case PPC::XOR8: in instrHasImmForm()
3921 case PPC::AND_rec: in instrHasImmForm()
3922 III.ImmOpcode = PPC::ANDI_rec; in instrHasImmForm()
3924 case PPC::AND8_rec: in instrHasImmForm()
3925 III.ImmOpcode = PPC::ANDI8_rec; in instrHasImmForm()
3927 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
3928 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; in instrHasImmForm()
3929 case PPC::XOR: III.ImmOpcode = PPC::XORI; break; in instrHasImmForm()
3930 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break; in instrHasImmForm()
3933 case PPC::RLWNM: in instrHasImmForm()
3934 case PPC::RLWNM8: in instrHasImmForm()
3935 case PPC::RLWNM_rec: in instrHasImmForm()
3936 case PPC::RLWNM8_rec: in instrHasImmForm()
3937 case PPC::SLW: in instrHasImmForm()
3938 case PPC::SLW8: in instrHasImmForm()
3939 case PPC::SLW_rec: in instrHasImmForm()
3940 case PPC::SLW8_rec: in instrHasImmForm()
3941 case PPC::SRW: in instrHasImmForm()
3942 case PPC::SRW8: in instrHasImmForm()
3943 case PPC::SRW_rec: in instrHasImmForm()
3944 case PPC::SRW8_rec: in instrHasImmForm()
3945 case PPC::SRAW: in instrHasImmForm()
3946 case PPC::SRAW_rec: in instrHasImmForm()
3956 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec || in instrHasImmForm()
3957 Opc == PPC::RLWNM8_rec) in instrHasImmForm()
3963 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
3964 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
3965 case PPC::RLWNM_rec: in instrHasImmForm()
3966 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
3968 case PPC::RLWNM8_rec: in instrHasImmForm()
3969 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
3971 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
3972 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
3973 case PPC::SLW_rec: in instrHasImmForm()
3974 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
3976 case PPC::SLW8_rec: in instrHasImmForm()
3977 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
3979 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
3980 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
3981 case PPC::SRW_rec: in instrHasImmForm()
3982 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
3984 case PPC::SRW8_rec: in instrHasImmForm()
3985 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
3987 case PPC::SRAW: in instrHasImmForm()
3990 III.ImmOpcode = PPC::SRAWI; in instrHasImmForm()
3992 case PPC::SRAW_rec: in instrHasImmForm()
3995 III.ImmOpcode = PPC::SRAWI_rec; in instrHasImmForm()
3999 case PPC::RLDCL: in instrHasImmForm()
4000 case PPC::RLDCL_rec: in instrHasImmForm()
4001 case PPC::RLDCR: in instrHasImmForm()
4002 case PPC::RLDCR_rec: in instrHasImmForm()
4003 case PPC::SLD: in instrHasImmForm()
4004 case PPC::SLD_rec: in instrHasImmForm()
4005 case PPC::SRD: in instrHasImmForm()
4006 case PPC::SRD_rec: in instrHasImmForm()
4007 case PPC::SRAD: in instrHasImmForm()
4008 case PPC::SRAD_rec: in instrHasImmForm()
4018 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR || in instrHasImmForm()
4019 Opc == PPC::RLDCR_rec) in instrHasImmForm()
4025 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4026 case PPC::RLDCL_rec: in instrHasImmForm()
4027 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4029 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4030 case PPC::RLDCR_rec: in instrHasImmForm()
4031 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4033 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4034 case PPC::SLD_rec: in instrHasImmForm()
4035 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4037 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4038 case PPC::SRD_rec: in instrHasImmForm()
4039 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4041 case PPC::SRAD: in instrHasImmForm()
4044 III.ImmOpcode = PPC::SRADI; in instrHasImmForm()
4046 case PPC::SRAD_rec: in instrHasImmForm()
4049 III.ImmOpcode = PPC::SRADI_rec; in instrHasImmForm()
4054 case PPC::LBZX: in instrHasImmForm()
4055 case PPC::LBZX8: in instrHasImmForm()
4056 case PPC::LHZX: in instrHasImmForm()
4057 case PPC::LHZX8: in instrHasImmForm()
4058 case PPC::LHAX: in instrHasImmForm()
4059 case PPC::LHAX8: in instrHasImmForm()
4060 case PPC::LWZX: in instrHasImmForm()
4061 case PPC::LWZX8: in instrHasImmForm()
4062 case PPC::LWAX: in instrHasImmForm()
4063 case PPC::LDX: in instrHasImmForm()
4064 case PPC::LFSX: in instrHasImmForm()
4065 case PPC::LFDX: in instrHasImmForm()
4066 case PPC::STBX: in instrHasImmForm()
4067 case PPC::STBX8: in instrHasImmForm()
4068 case PPC::STHX: in instrHasImmForm()
4069 case PPC::STHX8: in instrHasImmForm()
4070 case PPC::STWX: in instrHasImmForm()
4071 case PPC::STWX8: in instrHasImmForm()
4072 case PPC::STDX: in instrHasImmForm()
4073 case PPC::STFSX: in instrHasImmForm()
4074 case PPC::STFDX: in instrHasImmForm()
4084 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break; in instrHasImmForm()
4085 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break; in instrHasImmForm()
4086 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break; in instrHasImmForm()
4087 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break; in instrHasImmForm()
4088 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break; in instrHasImmForm()
4089 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break; in instrHasImmForm()
4090 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
4091 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break; in instrHasImmForm()
4092 case PPC::LWAX: in instrHasImmForm()
4093 III.ImmOpcode = PPC::LWA; in instrHasImmForm()
4096 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break; in instrHasImmForm()
4097 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break; in instrHasImmForm()
4098 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
4099 case PPC::STBX: III.ImmOpcode = PPC::STB; break; in instrHasImmForm()
4100 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break; in instrHasImmForm()
4101 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
4102 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break; in instrHasImmForm()
4103 case PPC::STWX: III.ImmOpcode = PPC::STW; break; in instrHasImmForm()
4104 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break; in instrHasImmForm()
4105 case PPC::STDX: in instrHasImmForm()
4106 III.ImmOpcode = PPC::STD; in instrHasImmForm()
4109 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break; in instrHasImmForm()
4110 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
4113 case PPC::LBZUX: in instrHasImmForm()
4114 case PPC::LBZUX8: in instrHasImmForm()
4115 case PPC::LHZUX: in instrHasImmForm()
4116 case PPC::LHZUX8: in instrHasImmForm()
4117 case PPC::LHAUX: in instrHasImmForm()
4118 case PPC::LHAUX8: in instrHasImmForm()
4119 case PPC::LWZUX: in instrHasImmForm()
4120 case PPC::LWZUX8: in instrHasImmForm()
4121 case PPC::LDUX: in instrHasImmForm()
4122 case PPC::LFSUX: in instrHasImmForm()
4123 case PPC::LFDUX: in instrHasImmForm()
4124 case PPC::STBUX: in instrHasImmForm()
4125 case PPC::STBUX8: in instrHasImmForm()
4126 case PPC::STHUX: in instrHasImmForm()
4127 case PPC::STHUX8: in instrHasImmForm()
4128 case PPC::STWUX: in instrHasImmForm()
4129 case PPC::STWUX8: in instrHasImmForm()
4130 case PPC::STDUX: in instrHasImmForm()
4131 case PPC::STFSUX: in instrHasImmForm()
4132 case PPC::STFDUX: in instrHasImmForm()
4142 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break; in instrHasImmForm()
4143 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break; in instrHasImmForm()
4144 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break; in instrHasImmForm()
4145 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break; in instrHasImmForm()
4146 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break; in instrHasImmForm()
4147 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break; in instrHasImmForm()
4148 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break; in instrHasImmForm()
4149 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break; in instrHasImmForm()
4150 case PPC::LDUX: in instrHasImmForm()
4151 III.ImmOpcode = PPC::LDU; in instrHasImmForm()
4154 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break; in instrHasImmForm()
4155 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break; in instrHasImmForm()
4156 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break; in instrHasImmForm()
4157 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break; in instrHasImmForm()
4158 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break; in instrHasImmForm()
4159 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break; in instrHasImmForm()
4160 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break; in instrHasImmForm()
4161 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break; in instrHasImmForm()
4162 case PPC::STDUX: in instrHasImmForm()
4163 III.ImmOpcode = PPC::STDU; in instrHasImmForm()
4166 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break; in instrHasImmForm()
4167 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break; in instrHasImmForm()
4174 case PPC::LXVX: in instrHasImmForm()
4175 case PPC::LXSSPX: in instrHasImmForm()
4176 case PPC::LXSDX: in instrHasImmForm()
4177 case PPC::STXVX: in instrHasImmForm()
4178 case PPC::STXSSPX: in instrHasImmForm()
4179 case PPC::STXSDX: in instrHasImmForm()
4180 case PPC::XFLOADf32: in instrHasImmForm()
4181 case PPC::XFLOADf64: in instrHasImmForm()
4182 case PPC::XFSTOREf32: in instrHasImmForm()
4183 case PPC::XFSTOREf64: in instrHasImmForm()
4196 case PPC::LXVX: in instrHasImmForm()
4197 III.ImmOpcode = PPC::LXV; in instrHasImmForm()
4200 case PPC::LXSSPX: in instrHasImmForm()
4203 III.ImmOpcode = PPC::LXSSP; in instrHasImmForm()
4205 III.ImmOpcode = PPC::LFS; in instrHasImmForm()
4211 case PPC::XFLOADf32: in instrHasImmForm()
4212 III.ImmOpcode = PPC::DFLOADf32; in instrHasImmForm()
4214 case PPC::LXSDX: in instrHasImmForm()
4217 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
4219 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
4225 case PPC::XFLOADf64: in instrHasImmForm()
4226 III.ImmOpcode = PPC::DFLOADf64; in instrHasImmForm()
4228 case PPC::STXVX: in instrHasImmForm()
4229 III.ImmOpcode = PPC::STXV; in instrHasImmForm()
4232 case PPC::STXSSPX: in instrHasImmForm()
4235 III.ImmOpcode = PPC::STXSSP; in instrHasImmForm()
4237 III.ImmOpcode = PPC::STFS; in instrHasImmForm()
4243 case PPC::XFSTOREf32: in instrHasImmForm()
4244 III.ImmOpcode = PPC::DFSTOREf32; in instrHasImmForm()
4246 case PPC::STXSDX: in instrHasImmForm()
4249 III.ImmOpcode = PPC::STXSD; in instrHasImmForm()
4251 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
4257 case PPC::XFSTOREf64: in instrHasImmForm()
4258 III.ImmOpcode = PPC::DFSTOREf64; in instrHasImmForm()
4332 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO && in isUseMIElgibleForForwarding()
4333 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8) in isUseMIElgibleForForwarding()
4350 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
4413 if (DefMI.getOpcode() == PPC::ADDItocL) { in isImmElgibleForForwarding()
4462 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4490 case PPC::CMPWI: in simplifyToLI()
4491 case PPC::CMPLWI: in simplifyToLI()
4492 case PPC::CMPDI: in simplifyToLI()
4493 case PPC::CMPLDI: { in simplifyToLI()
4511 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8) in simplifyToLI()
4518 if (RegToCopy == PPC::NoRegister) in simplifyToLI()
4521 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { in simplifyToLI()
4522 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); in simplifyToLI()
4533 CompareUseMI.setDesc(get(PPC::COPY)); in simplifyToLI()
4550 case PPC::ADDI: in simplifyToLI()
4551 case PPC::ADDI8: { in simplifyToLI()
4556 Is64BitLI = Opc == PPC::ADDI8; in simplifyToLI()
4562 case PPC::SUBFIC: in simplifyToLI()
4563 case PPC::SUBFIC8: { in simplifyToLI()
4570 Is64BitLI = Opc == PPC::SUBFIC8; in simplifyToLI()
4576 case PPC::RLDICL: in simplifyToLI()
4577 case PPC::RLDICL_rec: in simplifyToLI()
4578 case PPC::RLDICL_32: in simplifyToLI()
4579 case PPC::RLDICL_32_64: { in simplifyToLI()
4583 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32, in simplifyToLI()
4592 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) { in simplifyToLI()
4594 Is64BitLI = Opc != PPC::RLDICL_32; in simplifyToLI()
4596 SetCR = Opc == PPC::RLDICL_rec; in simplifyToLI()
4601 case PPC::RLWINM: in simplifyToLI()
4602 case PPC::RLWINM8: in simplifyToLI()
4603 case PPC::RLWINM_rec: in simplifyToLI()
4604 case PPC::RLWINM8_rec: { in simplifyToLI()
4616 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) && in simplifyToLI()
4620 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4622 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4627 case PPC::ORI: in simplifyToLI()
4628 case PPC::ORI8: in simplifyToLI()
4629 case PPC::XORI: in simplifyToLI()
4630 case PPC::XORI8: { in simplifyToLI()
4633 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
4639 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8; in simplifyToLI()
4717 assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) && in transformToNewImmFormFedByAdd()
4869 if (DefMI.getOpcode() == PPC::ADDItocL) in transformToImmFormFedByAdd()
4921 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in transformToImmFormFedByLI()
4957 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) && in transformToImmFormFedByLI()
4960 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) && in transformToImmFormFedByLI()
4971 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec || in transformToImmFormFedByLI()
4972 Opc == PPC::SRW || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
4973 Opc == PPC::SLW8 || Opc == PPC::SLW8_rec || in transformToImmFormFedByLI()
4974 Opc == PPC::SRW8 || Opc == PPC::SRW8_rec; in transformToImmFormFedByLI()
4975 bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec || in transformToImmFormFedByLI()
4976 Opc == PPC::SRD || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
4977 bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
4978 Opc == PPC::SLD_rec || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
4979 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD || in transformToImmFormFedByLI()
4980 Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5003 MI.setDesc(get(PPC::COPY)); in transformToImmFormFedByLI()
5052 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
5053 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; in transformToImmFormFedByLI()
5070 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
5071 return &PPC::VSRCRegClass; in updatedRC()
5076 return PPC::getRecordFormOpcode(Opcode); in getRecordFormOpcode()
5084 if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS || in isSignExtendingOp()
5085 Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec || in isSignExtendingOp()
5086 Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA || in isSignExtendingOp()
5087 Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 || in isSignExtendingOp()
5088 Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 || in isSignExtendingOp()
5089 Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX || in isSignExtendingOp()
5090 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU || in isSignExtendingOp()
5091 Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isSignExtendingOp()
5092 Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 || in isSignExtendingOp()
5093 Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in isSignExtendingOp()
5094 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB || in isSignExtendingOp()
5095 Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH || in isSignExtendingOp()
5096 Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 || in isSignExtendingOp()
5097 Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW || in isSignExtendingOp()
5098 Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 || in isSignExtendingOp()
5099 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 || in isSignExtendingOp()
5100 Opcode == PPC::EXTSB8_32_64) in isSignExtendingOp()
5103 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33) in isSignExtendingOp()
5106 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in isSignExtendingOp()
5107 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) && in isSignExtendingOp()
5121 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in isZeroExtendingOp()
5122 Opcode == PPC::LIS || Opcode == PPC::LIS8) { in isZeroExtendingOp()
5130 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in isZeroExtendingOp()
5131 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec || in isZeroExtendingOp()
5132 Opcode == PPC::RLDICL_32_64) && in isZeroExtendingOp()
5136 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in isZeroExtendingOp()
5141 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in isZeroExtendingOp()
5142 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in isZeroExtendingOp()
5143 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in isZeroExtendingOp()
5148 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in isZeroExtendingOp()
5149 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in isZeroExtendingOp()
5150 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 || in isZeroExtendingOp()
5151 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || in isZeroExtendingOp()
5152 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec || in isZeroExtendingOp()
5153 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW || in isZeroExtendingOp()
5154 Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec || in isZeroExtendingOp()
5155 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI || in isZeroExtendingOp()
5156 Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI || in isZeroExtendingOp()
5157 Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX || in isZeroExtendingOp()
5158 Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX || in isZeroExtendingOp()
5159 Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX || in isZeroExtendingOp()
5160 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ || in isZeroExtendingOp()
5161 Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in isZeroExtendingOp()
5162 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 || in isZeroExtendingOp()
5163 Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 || in isZeroExtendingOp()
5164 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 || in isZeroExtendingOp()
5165 Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in isZeroExtendingOp()
5166 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isZeroExtendingOp()
5167 Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec || in isZeroExtendingOp()
5168 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec || in isZeroExtendingOp()
5169 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec || in isZeroExtendingOp()
5170 Opcode == PPC::MFVSRWZ) in isZeroExtendingOp()
5184 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in isTOCSaveMI()
5208 case PPC::COPY: { in isSignOrZeroExtended()
5230 if (SrcReg == PPC::X3) { in isSignOrZeroExtended()
5235 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) { in isSignOrZeroExtended()
5264 case PPC::ANDI_rec: in isSignOrZeroExtended()
5265 case PPC::ANDIS_rec: in isSignOrZeroExtended()
5266 case PPC::ORI: in isSignOrZeroExtended()
5267 case PPC::ORIS: in isSignOrZeroExtended()
5268 case PPC::XORI: in isSignOrZeroExtended()
5269 case PPC::XORIS: in isSignOrZeroExtended()
5270 case PPC::ANDI8_rec: in isSignOrZeroExtended()
5271 case PPC::ANDIS8_rec: in isSignOrZeroExtended()
5272 case PPC::ORI8: in isSignOrZeroExtended()
5273 case PPC::ORIS8: in isSignOrZeroExtended()
5274 case PPC::XORI8: in isSignOrZeroExtended()
5275 case PPC::XORIS8: { in isSignOrZeroExtended()
5290 case PPC::OR: in isSignOrZeroExtended()
5291 case PPC::OR8: in isSignOrZeroExtended()
5292 case PPC::ISEL: in isSignOrZeroExtended()
5293 case PPC::PHI: { in isSignOrZeroExtended()
5300 if (MI.getOpcode() == PPC::PHI) { in isSignOrZeroExtended()
5323 case PPC::AND: in isSignOrZeroExtended()
5324 case PPC::AND8: { in isSignOrZeroExtended()
5357 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ)); in isBDNZ()
5375 if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) in PPCPipelinerLoopInfo()
5394 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR, in createTripCountGreaterCondition()
5410 if (LoopCount->getOpcode() == PPC::LI8 || in adjustTripCount()
5411 LoopCount->getOpcode() == PPC::LI) { in adjustTripCount()
5454 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop); in findLoopInstr()